A 10‐bit 1GSample/s hybrid digital‐to‐analog converter with a modified thermometer decoder in 65‐nm CMOS technology

Abstract

This paper proposes a new 10-bit 1GS/s digital-to-analog converter (DAC). In the proposed DAC configuration, a beneficial combination of differential resistor ladder and current sources is utilized to attain a significant reduction of the number of unit current sources. Therefore, the suggested 10-bit DAC is constructed based on only 21 current sources and 64 unit resistors, which results in a considerable decrease regarding the occupied area and power consumption. Also, a modified 4-bit thermometer decoder using a low number of transistors, based on SET-RST D flip-flops (SR-DFFs), is offered to drive the unit current sources synchronously. The proposed DAC is simulated in 65-nm Complementary metal oxide semiconductor (CMOS) technology. The postlayout simulation results indicate the better integral nonlinearity (INL) and differential nonlinearity (DNL) parameters than 0.3 least significant bit (LSB) and 0.6 LSB, respectively. Based on achieved results, the proposed DAC consumes 9.31 mW using a single supply voltage of 1.2 V. Moreover, the spuriousfree dynamic range (SFDR) is above 57 dB over 600-MHz Nyquist bandwidth, by considering 0.0134 mm 2 its occupied area.

A 12‐bit SC3 partially segmented current steering DAC with improved SFDR and bandwidth

“…These are as follows: where BW and P total are bandwidth and total power consumption, respectively. where and are maximum output swing of DAC and input signal frequency at which SFDR is measured, respectively 23 In which and area are the operating frequency and active area of the DAC, respectively 23 …”

“…In which f ck and area are the operating frequency and active area of the DAC, respectively. 23 The performance of the proposed circuit is compared with the recently reported architecture in Table 2. It has been found that the proposed circuit offers high bandwidth with minimum power consumption.…”

Mismatch error compensation of hybrid CS‐DAC to achieve high figure of merit utilizing on‐chip self‐healing assisted swap‐enabled randomization technique

“…However, the presence of non-ideal mismatch components in the CS-DAC designs majorly contributes for the reduced performance and linearity. [1][2][3][4][5][6] Additionally, increase in resolution and frequency of operation further degrade the static and dynamic performances. [7][8][9][10] Though the effect of random mismatch can be reduced by using current cells with larger size transistors, in spite of that, this method increases the output capacitances.…”

“…In this context, the current steering DAC (CS‐DAC) is the suitable architecture due to its inherent advantages. However, the presence of non‐ideal mismatch components in the CS‐DAC designs majorly contributes for the reduced performance and linearity 1–6 . Additionally, increase in resolution and frequency of operation further degrade the static and dynamic performances 7–10 …”