A 10-bit 200-MS/s CMOS parallel pipeline A/D converter

Sumanen, L.; Waltari, M.; Halonen, K.

doi:10.1109/4.933460

Cited by 149 publications

(76 citation statements)

References 21 publications

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“…Thus, 1-bit architecture seems also to be optimal for low power when capacitor scaling is not used. Only if opamp power consumption is dominated by the slew rate instead of the GBW requirement may a higher stage resolution be justified [4].…”

Section: Opamp Bandwidthmentioning

confidence: 99%

“…The third prototype [4] is a 10-bit time-interleaved ADC, which is the result of work carried out jointly with Lauri Sumanen. The design of the S/H front-end, digital offset calibration, clock generation, and reference voltage buffering have been on author's responsibility and the architecture design as well as the development of the new comparator structure have been collaborative achievements.…”

Section: Organization Of the Thesis And Research Contributionsmentioning

confidence: 99%

“…The timing skew may originate from the circuit generating the clock signals for different channels or it may be due to different propagation delays to the sampling circuits. Skew can be most easily avoided by using a full-speed front-end sample-and-hold circuit [94,98,4], as illustrated in Figure 4.19. The ADC channels resample the output of the S/H when it is in a steady state, and so the timing of the channels is not critical.…”

Section: Problems and Solutionsmentioning

confidence: 99%

“…The offset can be rather easily calibrated using a mixed signal [101] or all-digital circuitry [93,4]. Calibrating the gain mismatch is also possible, but requires more complex circuitry than offset calibration [99,100].…”

Section: Problems and Solutionsmentioning

confidence: 99%

“…[95,96,97,98,99,100,101,102]. The implementation of a four-channel prototype, originally published in [4], will be described in Section 12.4.…”

Section: Time-interleaved Adcmentioning

confidence: 99%

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Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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Section: Opamp Bandwidthmentioning

confidence: 99%

Section: Organization Of the Thesis And Research Contributionsmentioning

confidence: 99%

Section: Problems and Solutionsmentioning

confidence: 99%

Section: Problems and Solutionsmentioning

confidence: 99%

“…[95,96,97,98,99,100,101,102]. The implementation of a four-channel prototype, originally published in [4], will be described in Section 12.4.…”

Section: Time-interleaved Adcmentioning

confidence: 99%

See 3 more Smart Citations

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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A/D and D/A Conversion Architectures and Techniques

Sonkusale

Zourntos

2005

Encyclopedia of RF and Microwave Engineering

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A/D and D/A Conversion Architectures and Techniques

Sonkusale,

Zourntos

2005

Encyclopedia of RF and Microwave Engineering

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This article is concerned with the data conversion subsystem that interfaces the front‐end and back‐end portions of the transceiver core. A data converter translates signals between analog and digital representations. Our emphasis is on data converters for mobile communication systems in which cost and power savings are a priority. Therefore, although much of our discussion is of a general nature, our presentation is geared toward CMOS integrated circuit implementation and applications with low to moderate bandwidths (e.g., communications with WCDMA, IEEE 802.11a/b, or Bluetooth protocols).

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A 10-bit 200-MS/s CMOS parallel pipeline A/D converter

Cited by 149 publications

References 21 publications

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

A/D and D/A Conversion Architectures and Techniques

A/D and D/A Conversion Architectures and Techniques

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