Three different CMOS dynamic comparator topologies for pipeline AID converters, resistive divider, differential pair, and charge distribution comparators, are analyzed. The topologies considered are fully differential, i.e. both sensing and reference voltage inputs are balanced, consist only of a single stage, and feature zero DC power dissipation with a built-in threshold adjusting input stage. Test structures of the comparators, fabricated in 0.35-pm CMOS process, are measured to determine the offset properties of the compared topologies.In a mixed signal circuit such as an ADC, fully differential analog signals are preferred to get a better power supply rejection and immunity to common mode noise. A number of single stage, fully differential dynamic comparator topologies, including differential reference voltages, for pipeline ADCs have been proposed [2, 3, 41. They dissipate power only when latched and their trip point can be adjusted by introducing imbalance in the transistor [2, 31 or capacitor sizing [4]. In this paper these three different dynamic comparator topologies are analyzed and the measured performance of four test structures is given.
RESISTIVE DIVIDER COMPARATOR 1. INTRODUCTIONComparators form the core of all A/D converter (ADC) architectures. Properties of the comparators, especially offset, speed, and current dissipation, have an essential effect on the accuracy and power consumption of the whole ADC. In pipeline ADCs, where concurrently operating low-resolution stages are cascaded, the specifications of the comparators of sub-ADCs are somewhat relaxed. Offset is not so critical a parameter when the commonly-used redundant sign digit (RSD) correction is applied [ 11. This simple correction algorithm can tolerate comparator offsets up to *V,,f/2b in a stage with b effective bits when the reference voltage is V&. Even for a low voltage design this is usually in the order of hundreds of millivolts if b 5 3. Thus, the power can be traded with accuracy by using dynamic comparators without any continuous time pre-amplification. This reduces power dissipation considerably. Very small transistors are preferred to minimize the area as well. As the dynamic comparators are turned off when inactive, they are inevitably voluntary to fairly large offsets, mainly as a result of transistor mismatch emphasized by the switching transients. In spite of the loose offset specification this might become a limiting factor in the ADC performance.The most important comparator specifications are offset, power consumption and immunity to noise and mismatch. The work was supported by Finnish National Technology Agency (TEKES), Nokia Networks and Nokia Foundation. 0-7803-7448-7/02/$17.00 02002 IEEE V -157A widely-used dynamic comparator in pipeline A/D converters is based on a differential sensing amplifier. This so called resistive divider dynamic comparator, presented in Fig. 1, was introduced in [2]. Transistors M1-M4, biased in linear region, adjust the threshold resistively and above them transistors M5-Ml2 form a l...
