Timing skew insensitive switching for double sampled circuits

Waltari, M.; Halonen, K.

doi:10.1109/iscas.1999.780619

Cited by 36 publications

(20 citation statements)

References 3 publications

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“…This S/H circuit will provide a sampled output (hold operation) for two sampling phases of the first-stage pipeline employing the time-shifted CDS. This double-sampling S/H circuit is insensitive to timing skew due to the use of a series master sampling switch [17]. The capacitor mismatches are alleviated due to inherent voltage-mode operation (i.e., sampled input voltage is "flipped" to the output).…”

Section: Double-sampling S/h Stagementioning

confidence: 99%

A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique

Li¹,

Moon

2004

IEEE J. Solid-State Circuits

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Abstract-A time-shifted correlated double sampling (CDS)technique is proposed in the design of a 10-bit 100-MS/s pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp blocks to be replaced by simple cascoded CMOS inverters. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. An efficient common-mode voltage control is introduced for pseudodifferential architecture which can further reduce power consumption. Fabricated in a 0.18-m CMOS process, the prototype 10-bit pipelined ADC occupies 2.5 mm 2 of active die area. With 1-MHz input signal, it achieves 65-dB SFDR and 54-dB SNDR at 100 MS/s. For 99-MHz input signal, the SFDR and SNDR are 63 and 51 dB, respectively. The total power consumption is 67 mW at 1.8-V supply, of which analog portion consumes 45 mW without any opamp current scaling down the pipeline.Index Terms-Analog-to-digital converter (ADC), correlated double sampling (CDS), data converter, high speed, low power, low voltage, pipeline.

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Section: Double-sampling S/h Stagementioning

confidence: 99%

A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique

Li¹,

Moon

2004

IEEE J. Solid-State Circuits

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“…The first two are double-sampled S/H circuits [11,10,9], the latter of which uses the developed skew-insensitive sampling structure. The third prototype [4] is a 10-bit time-interleaved ADC, which is the result of work carried out jointly with Lauri Sumanen.…”

Section: Organization Of the Thesis And Research Contributionsmentioning

confidence: 99%

“…The opamp is a single stage operational transconductance amplifier (OTA) and its input transistor is realized with a MOSFET biased in the saturation region. Thus, the transconductance is 9) where I D is the drain current, µ the carrier mobility, C ox the gate oxide capacitance, and W and L the channel width and length. The second form of the equation is written using the expression for the gate capacitance C G = C ox W L. The gate capacitance appears between the opamp input and the ground and thus has an effect on the transfer function.…”

Section: Saturated Mosfet In Strong Inversionmentioning

confidence: 99%

“…This technique, called double-sampling, was first introduced in [184]. It has been applied in various SC circuits such as filters, ∆Σ-modulators [185,186], pipelined ADCs [97,4], and S/H circuits [11,10,9,187].…”

Section: Double-samplingmentioning

confidence: 99%

“…To overcome the timing skew problem a modification, which makes the double-sampled circuits insensitive to the timing errors, has been proposed by the author in [9]. There, the idea is to perform the sampling with a single switch rather than two parallel switches.…”

Section: Skew-insensitive Circuitmentioning

confidence: 99%

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Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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A 14b 100-MS/s Time-Interleaved A/D Converter

Hakkarainen¹,

Aho²,

Sumanen³

et al. 2005

Analog Integr Circ Sig Process

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This article presents a 14-bit, 100-MS/s time-interleaved pipeline ADC, which samples input signal from 210-MHz IF-band. Digital self-calibration is employed to compensate gain mismatch and offset between timeinterleaved channels as well as mismatches arise from a single ADC channel. A timing skew-insensitive parallel S/H circuit is utilized in order to avoid timing skew between parallel ADC channels. The ADC, fabricated in a 0.35-µm BiCMOS (SiGe) takes an area of 10.2 mm 2 , reaches an ENOB of 11.4 bits with a 79.9-dB SFDR at 192.5-MHz input and draws 1.4 W from a 3.0-V supply.

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Timing skew insensitive switching for double sampled circuits

Cited by 36 publications

References 3 publications

A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique

A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

A 14b 100-MS/s Time-Interleaved A/D Converter

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