A 10 bit, 2Ms/s, 15 mW BiCMOS cyclic RSD A/D converter

Abstract

A 10 bit, 2 megasamples per second (Ms/s) BiCMOS cyclic analog to digital converter (ADC) is presented. The ADC is optimized for low power operation and employs digital error correction based on the redundant signed digit (RSD) principle to correct for gain and offset errors.

A capacitor mismatch insensitive technique for RSD cyclic ADC

“…Traditional implementation of switched capacitor (SC) redundant sign digit (RSD) cyclic ADC [1] consists of a sample-and-hold (S/H) stage along with a gain stage, comparators, and sub-digital-to-analog converter (sub-DAC), where two clock phases are required per bit decision, S/H stage holds the input signal during the whole two phases, while gain stage samples in first phase and transfers charge in second phase. Other architecture replaces S/H stage in the traditional implementation with another gain stage [2]. By this way along with addition of another sub-DAC and comparators, two bits are resolved for two clock phases.…”

Sampled charge reuse for power reduction in switched capacitor data converters

“…Such an approach was presented by Ginetti et al in [24]. In [39], Garrity and Rakers recognized that by using digital correction and eliminating the need of a dedicated S/H, the input S/H could be converted to a complete stage by adding another set of comparators and sub-DAC. This addition resulted in reducing the total conversion time for the ADC from n to n/2.…”