A 10-Gb/s Adaptive Look-Ahead Decision Feedback Equalizer With an Eye-Opening Monitor

Seong, Chang-Kyung; Rhim, Jinsoo; Choi, Woo-Young

doi:10.1109/tcsii.2012.2186366

Cited by 16 publications

(5 citation statements)

References 14 publications

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“…Ref. [7] and [8] has only one-dimensional analysis by either phase or voltage amplitude change only. In ref.…”

Section: Measured Resultsmentioning

confidence: 99%

“…An eye-opening monitor (EOM) is a way to measure the data. Thus after processing EOM information by a certain algorithm, filter's coefficient and clock timing can also be adjusted [7]- [11]. The typical block diagram for EOM feedback in the receiver is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

“…1. Histogram approach for monitoring the contour and dispersion of the eye-diagram is done by voltage amplitude control [7] and clock phase control [8]. In ref.…”

Section: Introductionmentioning

confidence: 99%

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Eye-open monitor using two-dimensional counter value profile

Son

Moon

Baek

et al. 2019

IEICE Electron. Express

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A simple eye-opening monitor (EOM) system based on two dimensional (2-D) counter-value profile is designed. The proposed EOM can be applied to adaptive equalizer coefficient control for better bit error rate (BER) performance in the high-speed serial interface. Input data is sampled 2048 times with 32 different clock phases on 32 different decision threshold amplitudes to the clocked comparator and the sampled outputs of '1' or '0' are recorded in the designated counter.The counter values at each phase and decision threshold amplitude are compared with a reference of 1024 for eye-opening monitor. The estimated eye-diagram is displayed on the monitor. Through the estimated eye-diagram, the optimal sampling timing can also be determined. The chip for sampling data and gathering the counter value has been designed through 180-nm CMOS process and 86 mW including I/O block is consumed on 2 Gb/s data rate.

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“…Ref. [7] and [8] has only one-dimensional analysis by either phase or voltage amplitude change only. In ref.…”

Section: Measured Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Eye-open monitor using two-dimensional counter value profile

Son

Moon

Baek

et al. 2019

IEICE Electron. Express

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show abstract

“…Comparing with the eye-opening monitor in [15], our design can compensate the bigger loss, and the adaptation part is realized on the chip. A proposed FOM is calculated by FOM � total power data rate * channel loss .…”

Section: Postsimulation Resultsmentioning

confidence: 99%

A 1.25–12.5 Gbps Adaptive CTLE with Asynchronous Statistic Eye-Opening Monitor

Cai

Zhao

Zhou

2018

Journal of Electrical and Computer Engineering

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The equalization of a large attenuation signal and multirate communication in high-speed serial interface is hard to balance. To overcome this difficulty, an adaptive equalization system with optimized eye-opening monitor is proposed. The designed eye-opening monitor is based on the asynchronous statistic eye diagram tracking algorithm, and the eye diagram is obtained by undersampling with the low-speed asynchronous clock. With the eye-opening monitor into the adaptive loop, an adaptive equalization system combined with continuous-time linear equalization (CTLE) is completed. And the inductor peaking technology is used to improve the capacity of compensation. With SMIC 28 nm CMOS process to achieve the overall design, the power consumption and core chip area are 12 mW @ 12.5 Gbps and 0.12 mm2, respectively. And postsimulation results show that it can offer compensation from 6 to 21 dB for 1.25–12.5 Gbps range of receiving data, which achieves a large range of data rate and channel loss, and its power efficiency is 0.046 pJ/bit/dB for the worst case, which is better than most previous works.

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“…Even though the 10 Gb/s equalizer in Ref. [10] has the smallest area and lowest power, it is implemented with a more advanced process and only has the function of post-cursor cancelation, while the equalizer in this paper can eliminate both pre-cursor and post-cursor ISI.…”

Section: Simulation and Measurement Resultsmentioning

confidence: 99%

A 6.25 Gb/s equalizer in 0.18 μm CMOS technology for high-speed SerDes

Zhang¹,

Hu²

2013

J. Semicond.

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This paper presents a 0.18 m CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer (FFE) and a two-tap half-rate decision feedback equalizer (DFE) in order to cancel both pre-cursor and post-cursor ISI. By employing an active-inductive peaking circuit for the delay line, the bandwidth of the FFE is increased and the area cost is minimized. CML-based circuits such as DFFs, summers and multiplexes all help to improve the speed of DFEs. Measurement results illustrate that the equalizer operates well when equalizing 6.25 Gb/s data is passed over a 30-inch channel with a loss of 22 dB and consumes 55.8 mW with the supply voltage of 1.8 V. The overall chip area including pads is 0.3 0.5 mm 2 .

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A 10-Gb/s Adaptive Look-Ahead Decision Feedback Equalizer With an Eye-Opening Monitor

Cited by 16 publications

References 14 publications

Eye-open monitor using two-dimensional counter value profile

Eye-open monitor using two-dimensional counter value profile

A 1.25–12.5 Gbps Adaptive CTLE with Asynchronous Statistic Eye-Opening Monitor

A 6.25 Gb/s equalizer in 0.18 μm CMOS technology for high-speed SerDes

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