A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector

Byun, Sangjin; Lee, Jyung Chan; Shim, Jae Hoon; Kim, Kwangjoon; Yu, Hyun-Kyu

doi:10.1109/jssc.2006.883334

Cited by 38 publications

(37 citation statements)

References 12 publications

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“…First, it has a simple architecture and the least number of building blocks among all the reported quarter-rate linear PD [13], [14], [18]. It consumes very low power because the clock tree design implemented in [13], which helps to phase align the clock, is not being implemented here. So, the propagation delay will be critical and it will be analyzed in detail in the next section.…”

Section: A Proposed Pd Architecture and Circuit Implementationmentioning

confidence: 99%

“…As the proposed PD does not use clock tree [13] to achieve low power design, the analysis of propagation delay becomes critical. This section provides equations to predict the characteristic curve and analyzes the changes in UP and DN pulse-widths due to variations in the propagation delay for various phase difference.…”

Section: B Analysis Of the Proposed Pdmentioning

confidence: 99%

“…The linear PDs reported in [10]- [12] are high speed halfrate PDs implemented in CMOS process. There are also several lower-rate linearPDsreportedinCMOStechnology.In [13], [14], quarter-rate PDs are reported while in [15], a 1/8 rate PD is shown. The main disadvantage of lower-rate linear PD is its complexity increases when the rate decreases.…”

Section: Introductionmentioning

confidence: 99%

“…The main disadvantage of lower-rate linear PD is its complexity increases when the rate decreases. This will involve additional circuits such as clock tree [13], [15] to compensate for the delay time and result in higher power consumption. Also, large number of outputs would require more charge pump blocks, which may lead to severe current mismatches in charge pump circuits.…”

Section: Introductionmentioning

confidence: 99%

“…3 shows the block diagrams of the proposed CDR circuit. It employs a dual-loop CDR architecture with a frequency tracking loop and a phase tracking loop which helps to prevent false locking [13], [16], [17]. The frequency tracking loop composes of a phase frequency detector (PFD), a charge pump (CP), a low pass filter (LPF), a quadrature voltage controlled oscillator (QVCO) and a frequency divider.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector

Tan

Yeo

Boon

et al. 2012

IEEE Trans. Circuits Syst. I

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This paper presents a 5-Gb/s dual-loop clock and data recovery (CDR) circuit with a compact quarter-rate linear phase detector (PD). The proposed PD not only reduces the complexity of the circuit structure but also employs an UP pulse-widening technique to circumvent the problem of existing narrow UP pulses. Meanwhile, it has the least number of output signals among all the other linear PDs with UP pulse-widening technique. It also provides a data recovery circuit to de-multiplex the input data with no systematic phase offset. An unbalanced charge pump (CP) is also proposed to compensate the unbalanced pulse-width of UP and DN pulses as well as the unequal number of signal between UP and DN pulses. A detailed propagation delay analysis and a set of equations to predict the characteristic curve of the proposed PD is given. In addition, a lock detector with hysteresis property is implemented to ensure proper switching of the loops. Fabricated in 0.18-CMOS technology, the circuit shows that the peak-to-peak jitter of the recovered clock is 30.4-ps and it consumes 71.9-mW from a 1.8 V supply.Index Terms-Charge Pump, Clock and Data Recovery (CDR), dual-loop, lock detector, Phase Detector (PD), quarter-rate architecture, 5-Gb/s.

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Section: A Proposed Pd Architecture and Circuit Implementationmentioning

confidence: 99%

Section: B Analysis Of the Proposed Pdmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector

Tan

Yeo

Boon

et al. 2012

IEEE Trans. Circuits Syst. I

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1–5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector

Byun

Son

Hwang

et al. 2013

IET Circuits, Devices & Systems

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This study presents a 1-5.6 Gb/s CMOS clock and data recovery (CDR) integrated circuit (IC) implemented in a 0.13 μm CMOS process. The CDR uses a half-rate linear phase detector (PD) of which static phase offset is compensated by an additional binary PD and a digital charge pump (CP) calibration block. During initialisation, the static phase offset is detected by the binary PD and the CP current is controlled accordingly to compensate the static phase offset. Also, the architecture of this CDR IC is designed for a clock embedded serial data interface which transfers CDR training clock patterns before normal random data signals. The implemented IC consumes 16-22 mA from a 1.2 V core supply for data rates of 1-5.6 Gb/s and 20 mA from a 3.3 V I/O supply for two preamplifiers and low-voltage differential signalling drivers. When the 2 31-1 pseudorandom binary sequence is used, the measured bit-error rate is better than 10-12 and the jitter tolerance is 0.3UI pp. The recovered clock jitter is 21.6 and 4.2 ps rms for 1 and 5.6 Gb/s data rates, respectively.

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0.97 mW/Gb/s, 4 Gb/s CMOS clock and data recovery IC with dynamic voltage scaling

Byun

2016

IET Circuits, Devices & Systems

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This paper presents a low-power complementary metal-oxide-semiconductor (CMOS) clock and data recovery (CDR) integrated circuit (IC) with dynamic voltage scaling (DVS) technique. When DVS is adopted, the power efficiency can be improved by selecting the low supply voltage as possible for a given bit rate. However, the supply voltage generated from a switching regulator such as a buck converter has the ripple voltage at the switching frequency so that the CDR performance may be degraded accordingly. Thus, in this study, the analysis on the relationship among the ripple voltage, the switching frequency and the jitter tolerance (JTOL) is carried out and the appropriate ripple voltage and switching frequency of the buck converter are chosen based on the analysis. Moreover, low supply voltage circuit techniques are carefully utilised for the design of the low-power CDR IC. The CDR IC, implemented in a 0.11 μm CMOS process, shows the power efficiency of 0.97 mW/Gb/s at 4 Gb/s including the buck converter. When 4 Gb/s 2 31 −1 pseudorandom binary sequence is used, the measured bit error rate is better than 10 −12 , the measured JTOL is 0.3 UI pp and the measured jitter of the recovered clock is 6.1 ps rms .

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A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector

Cited by 38 publications

References 12 publications

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector

1–5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector

0.97 mW/Gb/s, 4 Gb/s CMOS clock and data recovery IC with dynamic voltage scaling

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