A 10 Gb/s demultiplexer IC in 0.18 μm CMOS using current mode logic with tolerance to the threshold voltage fluctuation

Pandey

2010 Annual IEEE India Conference (INDICON)

2010

This paper proposes a new active shunt-peaked realization for MOS Current Mode Logic (MCML) based memory element. The circuit proposes the use of active inductors in shunt-peaking of MCML memory element. The technique of shunt-peaking offers a way of enhancing the performance of gates at high speed of operations. The benefit of the proposed circuit is verified by designing and simulating various MCML based memory elements with resistive, PMOS, feedback and active inductor load. An overall performance evaluation in terms of setup time, hold time and propagation delay from clock-to-Q has been done in PSPICE using 0.18µm TSMC CMOS technology parameters. For a power supply of 3.3 V and clock frequency of 1 GHz, the simulation results show an improvement of 13 to 25 percent in the values of delay parameters for active shunt-peaked memory element in comparison to other existing MCML based designs.

Section: B Other Modified Structuresmentioning

confidence: 99%

Shunt-peaking in MCML memory element design in 0.18μm CMOS technology

Pandey

2010 Annual IEEE India Conference (INDICON)

2010

2009 International Microwave Workshop Series on Signal Integrity and High-Speed Interconnects

“…The polysilicon load resistors cover a significant area. To reduce the area, PMOS loads operating in the triode (or linear) region are adopted as was done in [1], as shown in Figs. 2(c) and 3(b).…”

Section: Circuit Designmentioning

confidence: 99%

“…Applications of high-performance demultiplexers (DEMUXes) [1]- [6] have so far been limited chiefly to those that accept a design trade-off in favor of speed, such as fiberoptic communication systems. In typical optical wavelengthdivision multiplexing (WDM) systems, for example, perwavelength speed of 10 Gb/s or faster is required.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 20 Gb/s 1:4 DEMUX with Near-Rail-to-Rail Logic Swing in 90 nm CMOS process

Mineyama

Suzuki

Ito

et al. 2009

A 9.5 mW 20 Gb/s 40 x 70 /_m2 inductorless 1:4 DEMUX in 90 nm CMOS process is presented. In order to reduce power and area, the DEMUX uses a multi-phase clock architecture that requires a smaller number of latches operating at a slower clock rate than in the conventional tree architecture. To provide low-voltage scalability, the latches operate with a near-tail-to-rail logic swing. It is realized without significant speed penalty by adopting current-sourceless CML-type latches with unconventional settings. It offers a larger noise margin and elimination of logic level converters too. The well-balanced scalable design could possibly broaden the applications of high-speed SerDes in the coming ultralowvoltage many-core era.Index Terms -DEMUX, CMOS, multi-phase clock architecture, near-rail-to-rail logic swing I. INTRODUCTION Applications of high-performance demultiplexers (DEMUXes) [1]-[6] have so far been limited chiefly to those that accept a design trade-off in favor of speed, such as fiberoptic communication systems. In typical optical wavelengthdivision multiplexing (WDM) systems, for example, perwavelength speed of 10 Gb/s or faster is required. The conventional wisdom in gaining or maintaining speed of CML-type circuits, used in [1]-[6], has been to reduce the signal amplitude. A dilemma here is that the noise immunity might have to be traded off. Another problem is that current-mode logic (CML)-type circuits do not go well with the trend of lowering the supply voltage. As regards other factors than the speed, since as many DEMUXes as the wavelength multiplicity are needed in WDM systems, the power and area are also important considerations. We present a 1:4 DEMUX with near-rail-to-rail architecture that could offer a possible solution to the challenges in signal integrity and low-voltage scalability as well as in balancing the speed, power, and area.

The KIPS Transactions:PartA

“…형화로 인해 10 Gb/s 클럭 데이터 복원 회로 [1] , 6 Gb/s 디 멀티플렉서 [2] 와 같은 수 Gb/s의 시스템들이 저 전력이면서 위해서 MOS 전류모드(MOS current-mode logic) [3] 가 제안 되었다. 이 회로는 기존의 CMOS 회로보다 1.5배 정도 더 빠른 데이터 전송 속도를 갖지만, 역시 토글 주파수의 영향 을 받게 되어 일정 속도 이상에서는 정확한 동작을 할 수 없다.…”

unclassified

Design of a 20 Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic

Kim

2008

This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC 0.18㎛ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.