A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications

Ciarpi, Gabriele; Mestice, M.; Rossi, Daniele; Palla, F.; Saponara, Sergio

doi:10.1109/access.2023.3297515

Cited by 1 publication

(1 citation statement)

References 37 publications

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“…Hence, the solution we are contemplating involves upgrading the front-end serializers to the new data rate and linking them to rad-hard silicon photonics (SiPh) on the module. Several rad-hard 25G serializers [3] and Silicon Photonics (SiPh) [4,5] are currently underdevelopment. Nevertheless, implementing any of these solutions directly into our application presents challenges.…”

Section: Velo Readout Challengesmentioning

confidence: 99%

The LHCb VELO Upgrade II: design and development of the readout electronics

Fernández Prieto

2024

J. Inst.

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The LHCb collaboration proposes a Phase-II Upgrade of the detector, to be installed during the LHC Long Shutdown 4 (2032–2034). Operating in the HL-LHC environment poses significant challenges to the design of the upgraded detector, and in particular to its tracking system. The primary and secondary vertices reconstruction will become more difficult due to the increase, by a factor of 7.5, of the average number of interactions per bunch crossing. The performance of the VErtex LOcator (VELO), which is the tracking detector surrounding the interaction region, is essential to the success of this Phase-II Upgrade. Data rates are especially critical for the LHCb full software trigger, and with the expected higher particle flux, the VELO Upgrade-II detector will have to tolerate a dramatically increased data rate: assuming the same hybrid pixel design and detector geometry, the front-end electronics (ASICs) of the VELO Upgrade-II will have to cope with rates as high as 8 Ghits/s, with the hottest pixels reaching up to 500 khits/s. With this input rate, the data output from the VELO will exceed 30 Tbit/s, with potentially a further increase if more information is added to the read-out. This paper outlines the challenges being addressed and the solutions under investigation for reading out the VELO sub-detector.

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Section: Velo Readout Challengesmentioning

confidence: 99%

The LHCb VELO Upgrade II: design and development of the readout electronics

Fernández Prieto

2024

J. Inst.

View full text Add to dashboard Cite

show abstract

A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications

Cited by 1 publication

References 37 publications

The LHCb VELO Upgrade II: design and development of the readout electronics

The LHCb VELO Upgrade II: design and development of the readout electronics

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