A 10-Gb/s Reconfigurable CMOS Equalizer Employing a Transition Detector-Based Output Monitoring Technique for Band-Limited Serial Links

Design Techniques for High-Speed I/Os: Challenges and Opportunities

“…Alternatively, the opening of data eyes can be used to guide DFE search [71,72]. Eye-opening can be captured using an Eye-Opening Monitor (EOM) [73][74][75][76][77][78][79][80][81]. Jitter-based eye-opening monitors that minimize timing jitter at the edges of data eyes also emerged [82].…”

A 10-Gb/sec unclocked current-mode logic (CML) analog decision-feedback equalizer (ADFE) in 0.18-μm CMOS

“…The minimum voltage swing needed for the decision signals, V CP and V CM to completely switch the tap current, I TAP , to one side is given by V DECISION in (1) [3]. V CORR is expressed in (2). Knowing the maximum value of V CORR and R LOAD , the maximum I TAP that will be needed can be determined using (2) and the maximum value of V DECISION needed can be calculated using (1).…”

“…The forward filter taps are set to remove pre-cursor ISI. The variable gain blocks are implemented using a Gilbert cell topology and can provide bipolar gain of +1 to -1 [2]. The gain of the taps can be tuned using the control voltages VC 0 -VC 3 .…”

“…The product of the resistor and transistor and parasitic capacitances determines the signal delay. The delay cells can also be tuned depending on system requirements [2]. The control voltage V FF provides a degree of control to achieve the optimum delay value for equalization.…”

“…The control voltage V FF provides a degree of control to achieve the optimum delay value for equalization. The design of the linear filter building blocks has been described in a previous publication [2].…”