A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology

Mori, J.; Nagamatsu, M.; Hirano, M.; Tanaka, S.; Noda, Makoto; Toyoshima, Y.; Hashimoto, Kunihisa; Hayashida, Hiroshi; Maeguchi, K.

doi:10.1109/4.75061

Cited by 97 publications

(25 citation statements)

References 4 publications

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“…Another multiplier implementation which uses the Wallace tree approach is the 54;54-bit regularly structured tree multiplier [19], proposed by Goto et al From the architectural point of view, this multiplier is very similar to those that have been described here [17,18]. Goto's multiplier uses Booth recoding and a Wallace tree of 4 : 2 compressors.…”

Section: Regularly Structured Tree Multipliermentioning

confidence: 98%

“…Mori et al presented an improved version of their previous work in [18]. In this case, the size of the multiplier was increased to 54;54 bits, but the basic approach remained the same.…”

Section: Cmos Multiplier With Improved Parallel Structurementioning

confidence: 99%

“…An important instance of this type of multiplier is the work by Nagamatsu et al [17,18]. The main characteristic of these implementations is that the complete Wallace tree of compressors is built and it is operated in a fully combinational fashion.…”

Section: Cmos Multiplier With Improved Parallel Structurementioning

confidence: 99%

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Redundant arithmetic, algorithms and implementations

Gonzalez

Mazumder

2000

Integration

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Section: Regularly Structured Tree Multipliermentioning

confidence: 98%

“…Mori et al presented an improved version of their previous work in [18]. In this case, the size of the multiplier was increased to 54;54 bits, but the basic approach remained the same.…”

Section: Cmos Multiplier With Improved Parallel Structurementioning

confidence: 99%

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Redundant arithmetic, algorithms and implementations

Gonzalez

Mazumder

2000

Integration

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“…The comparison is in respect to speed, power and power delay product. Up to now, many studies are conducted on multi-operand adders [18]. By applying the multi-operand adders and parallel multiplication scheme and their combination, the author in [19] was able to design and introduce a fast multi-operand multiplier.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of a Three-operand Multiplier through Carbon Nanotube Technology

Reshadinezhad

Charmchi²,

Navi³

2015

IJMECS

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Abstract-Multiplication scheme is one of the most essential factors, which is time consuming. Designers and manufacturers of processors emphasis on methods which would not only perform the multiplication scheme in a rapid manner, but would reduce the physical aspect of the design as well; hence, a reduction in power consumption. Addition is one of the fundamental factors in multiplication. Pre-designing of circuits and transistors' levels used to be made through Metal Oxide Semiconductor Field Effect Transistor (MOSFET), but now, due to scaling and difficulties thereof, new technologies like Single Electron Transistor (SET), Quantum-dot Cellular Automata (QCA) and Carbon Nanotube Field Effect Transistor (CNFET) are introduced. Among the new technologies, CNFET has become center of attention due to similarities in electronic features in relation to MOSFET. A comparison made between CNFET with MOSFET technologies indicate that, power delay product (PDP) and power leakage can be less in nanotube transistors. Field effect transistor circuit's simulations are accomplished through HSPICE simulator. The simulation results indicate that this proposed Three-operand Carbon Nanotube Multiplier has a better performance in comparison with the threeoperand multiplication done on computers nowadays, which we call it classical multiplier in this article.

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“…Since this multiplier performs 12-bit multiplications, 6 partial products are generated. By employing the Wallace adder tree and a 4:2 compressor adder [7], only two addition stages are needed in order to add 6 partial products. This addition is performed in the form of a tournament by using the Wallace adder tree method.…”

Section: -Bit 12-bit Multipliermentioning

confidence: 99%

High-performance all-digital quadrature frequency synthesizer/mixer

Tang

Wang

Min

The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002.

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In this paper, a high-performance all-digital quadrature frequency synthesizer/mixer applied to QAM modulation and demodulation is presented, which synthesizes 12-bit sine and cosine waveforms with a spectral purity of -83.0dB. The synthesizer covers a bandwidth from dc to 100 MHz in steps of 0.0466Hz with a corresponding switching speed of 5 ns at 200MHz clock frequency. Also, it is capable of frequency, phase and quadrature amplitude modulation. In this design, an efficient ROM look-up table method for calculating the sine and cosine function is employed, and a compression algorithm that only calculates one-eighth sine function is adopted to reduce the volume of ROM. By taking advantage of sine and cosine symmetries, the size of the ROM look-up table is only 1/51 of that of traditional one. The resulting chip fabricated in 0.35um five-level metal CMOS process has a complexity of about 20,000 gates with core area of 2.00 1.00 mm 2 .

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A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology

Cited by 97 publications

References 4 publications

Redundant arithmetic, algorithms and implementations

Redundant arithmetic, algorithms and implementations

Design and Implementation of a Three-operand Multiplier through Carbon Nanotube Technology

High-performance all-digital quadrature frequency synthesizer/mixer

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