1988
DOI: 10.1109/4.90034
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A 100-MHz pipelined CMOS comparator

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Cited by 86 publications
(3 citation statements)
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“…Based on the mismatch model of the 0.18 m CMOS, V OS1; 2 is calculated to be 8.2 mV from Eq. (7). By adding this DC voltage source V OS1; 2 as shown in Fig.…”
Section: Simulation Resultsmentioning
confidence: 99%
“…Based on the mismatch model of the 0.18 m CMOS, V OS1; 2 is calculated to be 8.2 mV from Eq. (7). By adding this DC voltage source V OS1; 2 as shown in Fig.…”
Section: Simulation Resultsmentioning
confidence: 99%
“…A multistep converter topology (SAR or pipelined) does not allow for the implementation of the comparator pipelining technique. The latter is usually found in very high speed flash ADCs to give extra regeneration time for a very low probability of metastability design [33]. Thus, an SAR ADC has to consider the clock speed and the regeneration time available in each comparison cycle in order to evaluate the probability of a metastable state, and then the probability of an erroneous conversion.…”
Section: Metastability Analisysmentioning
confidence: 99%
“…The latched comparator is used for the clock signal and indicate digital output level, whether its differential input signal is positive or negative. A positive feedback mechanism to regenerate the analog input signal into a full scale digital signal is much faster and power efficient than performing multi-stage linear applications [4]. The preamplifier latch comparator [5], which combines an amplifier and a latch comparator can be obtained high speed and low power dissipation.…”
Section: Introductionmentioning
confidence: 99%