Design of Low Power and High Speed CMOS Comparator for A/D Converter Application

Yewale, Shubhara

doi:10.4236/wet.2012.32015

Cited by 15 publications

(5 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Inverting amplifier-based ultra-low power low offset current comparator is discussed in [16,20]. In this proposed method an identical inverting amplifier is introduced to produce the low-input offset current in a comparator.…”

Section: Literature Workmentioning

confidence: 99%

High resolution mutated dynamic precision power gated comparator for 9-bit SAR ADC

Thamaraimanalan¹,

Venkatesan

2022

Preprint

View full text Add to dashboard Cite

Comparator design is a major challenge during the implementation of high resolution SAR ADCs. In this research, a mutated dynamic power gated comparator is designed to achieve the SAR ADC with ultra-low power and enhanced gain. The proposed power gated comparator is designed using 45nm CMOS technology, and it is tested at 3.3V and 5V. High speed and low power are achieved through transistor sizing and power gating techniques. Mismatch of transistors, the offset value is appropriately calculated using the input resistance of the differential amplifier and trans conductance. Also, the offset cancellation and digital calibration techniques are included in the design to enhance the precision, and to improve the performance of ADCs. For the proposed comparator, phase margin, gain, ICMR, power consumption, offset voltage, slew rate, load capacitance, propagation delay, kickback noise, and settling time are compared with the conventional comparator. The proposed design consumes only 4.2mW while operating at 5V and 1.5mW when the input voltage is 3.3V. The effective resolution of the SAR ADC is observed as 8.2 bit with the proposed power gated comparator.

show abstract

Section: Literature Workmentioning

confidence: 99%

High resolution mutated dynamic precision power gated comparator for 9-bit SAR ADC

Thamaraimanalan¹,

Venkatesan

2022

Preprint

View full text Add to dashboard Cite

show abstract

“…In high-speed ADCs, the comparator design is highly critical to the overall system performance [12][13][14]. It is the main bottleneck in limiting the speed of a high-speed, high-resolution ADC.…”

Section: Comparatormentioning

confidence: 99%

12 bit 3.072 GS/s 32‐way time‐interleaved pipelined ADC with digital background calibration for wideband fully digital receiver application in 65 nm complementary metal–oxide–semiconductor

Siddiqui

Choi

2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

The performance of a wideband receiver is highly dependent on the performance of the analogue-to-digital converter (ADC) used. Such applications require ADCs to operate at ultra-high speeds with high accuracy for inputs ranging from 40 MHz-1 GHz. Conventional solutions either use filters and mixers to extract the frequency of interest and convert it using a low-speed ADC or use a single ultra-high-speed flash converter. Both of these solutions consume ultra-high power and require complex circuitry, which expands exponentially with the converter resolution. In this work, a 12 bit 3.072 GS/s time-interleaved pipeline ADC is proposed. In total, 32 pipeline ADCs, each with a sampling rate of 96 MS/s, are interleaved in the time domain to achieve an overall sampling rate of 3.072 GS/s. In addition to the potential energy-saving capabilities of a time-interleaving structure, the circuit adopts amplifier sharing in sample-and-hold circuits, further improving the power efficiency. To account for interleaving mismatch, the circuit uses a pure background calibration technique, maintaining the system linearity and spectral efficiency. The proposed design achieves signal-to-noise-and-distortion ratio of 53.65 dB and spurious-free dynamic range (SFDR) of 69.04 dB while consuming 820 mW of power at a 1.2 V supply, resulting in a figure-of-merit of 0.67 pJ/conv-step.

show abstract

“…Nowadays, latch comparators are widely adopted for various applications that require prompt and exact processing [9][10][11]. However, the latch comparators were not selected for this particular work.…”

Section: Comparatormentioning

confidence: 99%

Development of a Position Decoding ASIC for SPECT using Silicon Photomultiplier

et al. 2016

View full text Add to dashboard Cite

Design of Low Power and High Speed CMOS Comparator for A/D Converter Application

Cited by 15 publications

References 10 publications

High resolution mutated dynamic precision power gated comparator for 9-bit SAR ADC

High resolution mutated dynamic precision power gated comparator for 9-bit SAR ADC

12 bit 3.072 GS/s 32‐way time‐interleaved pipelined ADC with digital background calibration for wideband fully digital receiver application in 65 nm complementary metal–oxide–semiconductor

Development of a Position Decoding ASIC for SPECT using Silicon Photomultiplier

Contact Info

Product

Resources

About