Development of a Position Decoding ASIC for SPECT using Silicon Photomultiplier

Cho, Minkyu; Kim, Hyojoong; Lim, Kyung Taek; Cho, Gyuseong

doi:10.1088/1748-0221/11/01/c01065

Cited by 1 publication

(3 citation statements)

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“…In other words, channels of SIG0, SIG1, SIG2 and SIG3 corresponds to (00), (01), ( 10) and (11), respectively. Figure 6 shows the position pulses of seven valid signals corresponding to the time and energy pulses in figure 5; SIG1(01), SIG2(10), SIG3 (11), SIG3(11), SIG1(01), SIG2 (10), and SIG1(01) in sequence.…”

Section: Circuit Simulation Resultsmentioning

confidence: 99%

“…The reason for the delay is to insure that the rising edge of the time pulse is inside the enable pulse. The fixed delayed time can be optimally determined considering the timing resolution and efficiency of the PET system [10]. In this study, T d is set to be 30 ns.…”

Section: Design Of Vsspdamentioning

confidence: 99%

“…An ASIC chip for a 1-channel SiPM has been developed specifically for SPECT [10]. Thus, the goal of this work is to extend it to a 16-to-1 channel reducing ASIC for PET.…”

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confidence: 99%

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A design of a valid signal selecting and position decoding ASIC for PET using silicon photomultipliers

et al. 2017

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In most cases, a PET system has numerous electrical components and channel circuits and thus it would rather be a bulky product. Also, most existing systems receive analog signals from detectors which make them vulnerable to signal distortions. For these reasons, channel reduction techniques are important. In this work, an ASIC for PET module is being proposed. An ASIC chip for 16 PET detector channels, VSSPDC, has been designed and simulated. The main function of the chip is 16-to-1 channel reduction, i.e., finding the position of only the valid signals, signal timing, and magnitudes in all 16 channels at every recorded event. The ASIC comprises four of 4-channel modules and a 2 nd 4-to-1 router. A single channel module comprises a transimpedance amplifier for the silicon photomultipliers, dual comparators with high and low level references, and a logic circuitry. While the high level reference was used to test the validity of the signal, the low level reference was used for the timing. The 1-channel module of the ASIC produced an energy pulse by time-over-threshold method and it also produced a time pulse with a fixed delayed time. Since the ASIC chip outputs only a few digital pulses and does not require an external clock, it has an advantage over noise properties. The cadence simulation showed the good performance of the chip as designed.

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Section: Circuit Simulation Resultsmentioning

confidence: 99%

Section: Design Of Vsspdamentioning

confidence: 99%