A 100-MS/s 8-b CMOS subranging ADC with sustained parametric performance from 3.8 V down to 2.2 V

Abstract

A 100-MS/s 8-b CMOS analog-to-digital converter (ADC) designed for very low supply voltage and power dissipation is presented. This single-ended-input ADC is based on the unified two-step subranging architecture, which processes the coarse and fine decisions in identical signal paths to maximize their matching. However, to minimize power and area, the coarse-to-fine overlap correction has been aggressively reduced to only one LSB. The ADC incorporates five established design techniques to maximize performance: bottom-plate sampling, distributed sampling, auto-zeroing, interpolation, and interleaving. Very low voltage operation required for a general purpose ADC was obtained with four additional and new circuit techniques. These are a dual-gain first-stage amplifier, differential T-gate boosting, a supply independent delay generator, and a digital delay-locked-loop controlled output driver. For a clock rate of 100 MS/s, 7.0 (7.3) effective bits for a 50 MHz (10 MHz) input are maintained from 3.8 V down to 2.2 V. At 2.2 V, this 100-MS/s converter dissipates 75 mW plus 9 mW for the reference ladder. For a typical supply of 2.7 V, it consumes just 1 mW per MS/s over the 10-160-MS/s clock frequency range. Differential nonlinearity below 0.5 LSB is maintained from 2.7 V down to 2.2 V, and it degrades only slightly to 0.8 LSB at 3.8-V supply. The converter is implemented in a 0.35-mm CMOS process, with double-poly capacitors and no low-threshold devices.

Recent Advances and Trends in High-Performance Embedded Data Converters

“…Figure 16 illustrates another variation of the subranging architecture, where the same quantizer is re-used cyclically [55,56]. Note that in case of N C = 1 bit this reduces to the SAR ADC (conversion takes N cycles), and for N C = N bit it becomes the full-flash ADC (conversion takes 1 cycle).…”

An Offset Compensated Sampled-Data CMOS Comparator Circuit for Low-Power Implantable Biosensor Applications

“…C ip is approximately the sum of the gate-to-source capacitances of the driver and load devices of the single-ended inverter-amplifier. In conjunction with C1, inverter-amplifier 1 thus performs a dynamic sample and hold function for this comparator circuit [5,14]. Due to electrostatic coupling of only the difference signal, (V 1 − V 2), both the inputs V 1 and V 2 can individually vary over a wide dynamic range.…”

“…The final output is latched via cross-coupled NAND gates. Based on the above description, when compared to the inverter-comparators in subranging [5,14] and pipelined [9] analog-to-digital converters, the proposed comparator is a novel single-ended cascade of a front-end two-stage chopper-inverter comparator [10] and a back-end sampled data differential amplifier, which is able to provide considerable input offset compensation. The back-end differential comparatoramplifier loads its signals under comparison at the negative and positive input terminals in discrete-time sampled-data mode during intervals PH1 and PH2 respectively using a single-ended connection with inverter-amplifier 2.…”

“…The inverter-amplifiers are designed using relatively long channel devices to obtain a higher output impedance and resulting higher voltage gain. Unlike the inverters in [14] which use a separate bias generation for the positive channel MOS (PMOS) device, the inverters in the proposed circuit are self-biased dynamically during PH1 by shorting to the output and forming a diode voltage divider. The problem of charge injection and charge absorption along the signal path is minimized by using dummy pass gates.…”

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

“…With CMOS technology a sampling rate as high as 100 MS/s with 8-bit resolution has been reported in [51], while 12-bit resolution at 54 MS/s has been achieved in [52]. Figure 4.7 shows the idea of folding.…”