A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

Liu, Chun-Cheng; Chang, Soon-Jyh; Huang, Guan-Ying; Lin, Ying-Zu; Huang, Chung-Ming; Huang, Chih‐Hao; Bu, Linkai; Tsai, Cheng-Chia

doi:10.1109/isscc.2010.5433970

Cited by 182 publications

(88 citation statements)

References 2 publications

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“…4-21. It is seen that the SAR logic forms the dominant source of power consumption which agrees well with that of SAR ADCs with similar specification reported in [68], [9], [89], [90]. Post-layout simulation of the ADC including device noise was performed for the typical and worst PVT corners with near-Nyquist differential inputs and a sampling rate of 50 MS/s.…”

Section: Simulation Resultssupporting

confidence: 77%

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Harikumar¹

2016

Linköping Studies in Science and Technology. Dissertations

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Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless sensor networks (WSNs), wireless/wireline communication receivers and data acquisition systems. To achieve long-term, autonomous operation for WSNs, the nodes are powered by harvesting energy from ambient sources such as solar energy, vibrational energy etc. Since the signal frequencies in these distributed WSNs are often low, ultra-low-power ADCs with low sampling rates are required. The advent of new wireless standards with ever-increasing data rates and bandwidth necessitates ADCs capable of meeting the demands. Wireless standards such as GSM, GPRS, LTE and WLAN require ADCs with several tens of MS/s speed and moderate resolution (8-10 bits). Since these ADCs are incorporated into battery-powered portable devices such as cellphones and tablets, low power consumption for the ADCs is essential.The first contribution is an ultra-low-power 8-bit, 1 kS/s successive approximation register (SAR) ADC that has been designed and fabricated in a 65-nm CMOS process. The target application for the ADC is an autonomously-powered soil-moisture sensor node. At V DD = 0.4 V, the ADC consumes 717 pW and achieves an FoM = 3.19 fJ/conv-step while meeting the targeted dynamic and static performance. The 8-bit ADC features a leakage-suppressed S/H circuit with boosted control voltage which achieves > 9-bit linearity. A binary-weighted capacitive array digital-to-analog converter (DAC) is employed with a very low, custom-designed unit capacitor of 1.9 fF. Consequently the area of the ADC and power consumption are reduced. The ADC achieves an ENOB of 7.81 bits at near-Nyquist input frequency. The core area occupied by the ADC is only 0.0126 mm 2 .The second contribution is a 1.2 V, 10 bit, 50 MS/s SAR ADC designed and implemented in 65 nm CMOS aimed at communication applications. For medium-tohigh sampling rates, the DAC reference settling poses a speed bottleneck in chargeredistribution SAR ADCs due to the ringing associated with the parasitic inductances. Although SAR ADCs have been the subject of intense research in recent years, scant attention has been laid on the design of high-performance on-chip reference voltage buffers. The estimation of important design parameters of the buffer as well iv critical specifications such as power-supply sensitivity, output noise, offset, settling time and stability have been elaborated upon in this dissertation. The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages. The 10-bit SAR ADC utilizes split-array capacitive DACs to reduce area and power consumption. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the ...

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Section: Simulation Resultssupporting

confidence: 77%

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Harikumar¹

2016

Linköping Studies in Science and Technology. Dissertations

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“…In its simplest form, extra stage redundancy can be implemented by replicating one or more stages in a multistage ADC and appropriately adjusting the digital summation block [24], [25]. Recently, more advanced techniques for SAR ADCs have been explored that preshift the input signal to allow for digital recombination that looks much like half-bit redundancy [26].…”

Section: Extra Stage Redundancymentioning

confidence: 99%

The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping

Guerber

Gande

Moon

2012

IEEE Trans. Circuits Syst. I

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Abstract-An analysis of the statistics of multistage (pipeline, SAR, and algorithmic) ADCs with redundancy is performed and the ability to achieve an extra 6 dB of resolution in ADCs with half-bit redundancy is shown due to probability density function (PDF) residue shaping. This paper classifies redundancy techniques to show that only some have properties leading to statistical resolution improvements. When properly implemented, resolution gains are maintained even in the presence of large sub-ADC nonlinearity. ADC design criteria for maximizing these resolution increases through PDF residue shaping are described including improved back-end ADCs, stage comparator offset bounds, and the use of scaled conventional restoring with Z added levels (CRZ) stage redundancy. PDF residue shaped structural improvements are also quantified in relation to ideal and nonideal traditional multistage ADC structures.

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“…For a 100 MS/s 10 bit SAR ADC with a bit cycle of 600 ps [2], the conventional SAR logic delay takes about 270 ps (according to simulation results from the replica of [1]), which becomes a bottleneck to increase speed. Simulation results show that T XOR can be non-ignorable: about 80 ps because the XOR drives 10 fast DFFs in the shift register.…”

Section: Conventional and Precharge-evaluate Sar Logicmentioning

confidence: 99%

“…In recent years, several novel techniques to increase speed are reported. For example, asynchronous timing [1,2,3] and "2-bit per cycle" [4,5], redundant bit correction (over-range) [2] and split-capacitor array [5] and so on. Many techniques concentrates on systematic timing control, or rapid DAC settling, however, the speed enhancing of the SAR logic has been discussed much less.…”

Section: Introductionmentioning

confidence: 99%

A fast low power window-opening logic for high speed SAR ADC

Fan

Sun

et al. 2014

IEICE Electron. Express

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A new window-opening low-power area-efficient switching logic for high speed successive approximation register (SAR) analog-todigital converter (ADC) is proposed in this paper. Unlike conventional SAR logic based on the shift register, the window-opening scheme minimizes the delay by putting the comparator results almost directly to DAC, and utilizes domino-based structure to reduce the capacitive load for comparator. According to pre-layout simulation in 65 nm CMOS technology, a 10 bit 100 MS/s SAR ADC with the new logic achieves a logic delay of 73 ps including DAC buffer delay, which is much lower than most SAR ADC.

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A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

Cited by 182 publications

References 2 publications

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping

A fast low power window-opening logic for high speed SAR ADC

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