Proceedings ISSCC '95 - International Solid-State Circuits Conference
DOI: 10.1109/isscc.1995.535556
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A 10b 3MSample/s CMOS cyclic ADC

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Cited by 7 publications
(2 citation statements)
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“…The Cyclic ADC conversion stage contains a 1 bit sub-ADC, a 1 bit digital-to-analog converter (DAC), an analog subtractor, and a gain amplifier [2]. This conversion stage resolves one bit and feedbacks the residual signal to the input node of Copyright c 2013 The Institute of Electronics, Information and Communication Engineers conversion stage again for next conversion step.…”
Section: β-Expasion Based Cyclic Adc Architecturementioning
confidence: 99%
See 1 more Smart Citation
“…The Cyclic ADC conversion stage contains a 1 bit sub-ADC, a 1 bit digital-to-analog converter (DAC), an analog subtractor, and a gain amplifier [2]. This conversion stage resolves one bit and feedbacks the residual signal to the input node of Copyright c 2013 The Institute of Electronics, Information and Communication Engineers conversion stage again for next conversion step.…”
Section: β-Expasion Based Cyclic Adc Architecturementioning
confidence: 99%
“…amplifier/comparator offset). As proposed in [2], cyclic ADC has one redundant bit at backend sub-ADC, so that the influence of offset error of amplifier and comparator can be cancelled by digital correction technique with the redundant bit. Pipeline ADC with 1.5 bit/stage architecture has been reported in [3], and the error correction using the redundant bit at each pipelined stage becomes the most popular technique for pipeline ADCs.…”
Section: Introductionmentioning
confidence: 99%