A 10Gbase Ethernet transceiver (LAN PHY) in a 1.8 V, 0.18 μm SOI/CMOS technology

Yoshimura, Tsutomu; Ueda, K.; Takasoh, Jun; Wada, Y.; Oka, T.; Kondoh, H.; Chiba, O.; Azekawa, Y.; Ishiwaki, M.

doi:10.1109/cicc.2002.1012840

Cited by 3 publications

(3 citation statements)

References 7 publications

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“…Separate TIAs and 3 V laser/modulator drivers have been fabricated in Si bipolar or SiGe HBT technologies [19]. Receivers, transmitters and transceivers, clocked at 5 GHz [6] or at 10 GHz [7], have also been realized in 0.18 µm SOI−CMOS, or 0.18 µm CMOS, respectively, but it is highly probable that 10 Gb/s 3V or 5V drivers will not be realizable in present or future generation Si CMOS. GaAs HBTs and p−HEMTs will retain the 5V modulator driver markets in long−haul SONET/SDH applications.…”

Section: Technology Choicesmentioning

confidence: 99%

A COMPARISON OF SILICON AND III–V TECHNOLOGY PERFORMANCE AND BUILDING BLOCK IMPLEMENTATIONS FOR 10 AND 40 Gb/s OPTICAL NETWORKING ICs

Voinigescu¹,

McPherson²,

Pera³

et al. 2003

Int. J. Hi. Spe. Ele. Syst.

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Scalable models for both active and passive components are essential for the design of highly integrated fiber–optic physical layer ICs. This paper focuses on the various technology options available of 10 Gb/s and 40 Gb/s applications, on how their constituent components are modeled and what the characteristics and requirements are for the basic building blocks. As part of the technology comparison, an overview of the performance of leading edge Si CMOS, SiGe BiCMOS and III–V technologies is presented. Scalable models for SiGe HBTs and GaAs p–HEMTs are then compared with measured data for various device sizes. Inductors, varactors, transmission lines and isolation techniques on Si and III–V substrates are discussed next followed by technology–specific implementations of VCO and digital building blacks. Finally, Transimpedance Limiting Amplifier (TIALA) as well as laser and modulator driver designs in SiGe BiCMOS, InP HBT and GaAs p–HEMT processes using scalable device models are illustrated for 10 and 40 Gb/s fiber-optics applications.

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Section: Technology Choicesmentioning

confidence: 99%

A COMPARISON OF SILICON AND III–V TECHNOLOGY PERFORMANCE AND BUILDING BLOCK IMPLEMENTATIONS FOR 10 AND 40 Gb/s OPTICAL NETWORKING ICs

Voinigescu¹,

McPherson²,

Pera³

et al. 2003

Int. J. Hi. Spe. Ele. Syst.

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“…In this paper, our SO1 deviceiprocess is presented and one of the actual examples which use the body-tied structure is presented [8].…”

Section: Introductionmentioning

confidence: 99%

SOI technology for future SoC

Inoue

2002

Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT.

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SO1 CMOS devices have been investigated for a long time and as the quality of SO1 wafers has been improved as the same level of bulk-Si wafers and improvement of the speed performance of C.MOS devices is becoming difficult, they have entered the phase ofpractical use.There are two approaches for the usage of SO1 CMOS. One approach is the SO1 CMOS in floating-body structure and the other is the one in body-tied structure. In the case of body-tied structure it is possible to realize the layout with the bulk-Si compatibility and to suppress the history effect due to the floating body structure.To keep the compatibility of bulk-Si CMOS technology, we developed the hybrid trench technology, which realizes the body-tied structure for each transistor and full isolation between NMOS and PMOS transistors.

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“…Particularly, the optical fiber links provide efficient solution for gigabit data rate, while traditional copper links hardly sustain increasing data rates due to its physical limitations [4], [5]. Yet the optical fiber link is still costly, and therefore, the physical layer designs of optical fiber links (e.g., optical receivers) are required to be based on low-cost and low-power strategies [6]- [10].…”

Section: Introductionmentioning

confidence: 99%

A 4-gb/s CMOS clock and data recovery circuit using 1 = 8 -rate clock technique

Song

Park

Yoo

2003

IEEE J. Solid-State Circuits

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A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-m standard CMOS technology. The CDR circuit exploits 1 8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output.A 1 8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 2 31 1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be 112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10 6 for 2 31 1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply.Index Terms-Clock and data recovery, CMOS, linear phase detector, optical receivers, voltage-controlled oscillator (VCO), 1 8-rate clock.

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A 10Gbase Ethernet transceiver (LAN PHY) in a 1.8 V, 0.18 μm SOI/CMOS technology

Cited by 3 publications

References 7 publications

A COMPARISON OF SILICON AND III–V TECHNOLOGY PERFORMANCE AND BUILDING BLOCK IMPLEMENTATIONS FOR 10 AND 40 Gb/s OPTICAL NETWORKING ICs

A COMPARISON OF SILICON AND III–V TECHNOLOGY PERFORMANCE AND BUILDING BLOCK IMPLEMENTATIONS FOR 10 AND 40 Gb/s OPTICAL NETWORKING ICs

SOI technology for future SoC

A 4-gb/s CMOS clock and data recovery circuit using 1 = 8 -rate clock technique

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