A 4-gb/s CMOS clock and data recovery circuit using 1 = 8 -rate clock technique

Abstract

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-m standard CMOS technology. The CDR circuit exploits 1 8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output.A 1 8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 2 31 1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be 112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10 6 for 2 31 1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply.Index Terms-Clock and data recovery, CMOS, linear phase detector, optical receivers, voltage-controlled oscillator (VCO), 1 8-rate clock.

A 20-Gb/s 1: 2 demultiplexer in 0.18-μm CMOS

“…III. The parallel-current-switching (PCS) configuration [12] and the folded CML latch [13] , where the clock switching pairs are folded and parallel with the data switching pairs.…”

“…Except for the standard CML latch and the folded CML latch, other latches suffer from shortcomings, such as more jitter, crosstalk, and worse common mode suppression characteristics. Moreover, the PCS latch and the folded CML latch exhibit a lower speed than standard CML latches [12,13] .…”

Design of a high speed and power efficient quarter-rate clock and data recovery circuit

“…It is also often known as acquisition range. For Gb/s CDR system, both the lock range and capture range will be in the range of a few-MHz to hundreds-MHz [36][37][38]. The required time for the CDR to lock, locking time, will be in the range of hundreds-ns to tens-µs [39][40][41][42].…”