A 10k-Cycling Reliable 90nm Logic NVM "eCFlash" (Embedded CMOS Flash) Technology

Shukuri, S.; Shimizu, Satoshi; Ajika, N.; Ogura, Takumi; Mihara, M.; Kawajiri, Y.; Kobayashi, Kazuo; Nakashima, M.

doi:10.1109/imw.2011.5873184

Cited by 7 publications

(3 citation statements)

References 7 publications

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“…Furthermore, they often need relatively high program voltage [39]- [41]. A few highdensity proposals (area ≤ 3 µm 2 ) can still be found: [42], [43] present compact solutions, limited to single-bit logic; in [44], a Y-shaped two-transistor device cell is presented, used in [13] as analog memory for neuromorphic computing. A single-MOSFET device is proposed in [45], where electrons or holes can be injected in the spacer of non-overlapped channel regions, with limited analog capability.…”

Section: Introductionmentioning

confidence: 99%

Time Domain Analog Neuromorphic Engine Based on High-Density Non-Volatile Memory in Single-Poly CMOS

2022

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Increasing the energy efficiency of deep learning systems is critical for improving the cognitive capability of edge devices, often battery operated, as well as for data centers, constrained by the total power envelope. Specialized architectures accelerated by analog vector-matrix multipliers (VMMs) can reduce by orders of magnitude the energy per operation, since the reduced precision of analog computation does not undermine the classification accuracy of the neural network. We show an analog vector-matrix multiplier fabricated with industry-standard 0.18 µm CMOS process, exploiting a single-transistor non-volatile analog memory cell and dedicated technology circuit co-design. The design is focused on implementation in neural networks performing offline training. The VMM performs the analog multiplication of a vector of inputs, encoded in the duration of time pulses, times a matrix of weights, encoded in the programmable currents of the memory cells. A 1.72 µm 2 memory cell is realized with a single transistor with floating gate, which can be operated as a two-terminal analog memristive device with more than 64 programmable current levels and high I high /I low ratio (> 10 3 ), tuned by the charge injected in the floating gate. A small-area charge amplifier is used to convert the multiply and accumulate operation result into a voltage. System-level projections based on our measurements and simulations provide a throughput of 333.17 GOps/s and an energy efficiency of 122.3 TOps/J, higher than comparable-precision VMMs reported in the literature, and an equivalent area per cell down to 2.15 µm 2 , lower than any similar state-ofthe-art solution. Of critical importance in view of translation to industry, our proposal uses in a new way an industry-standard low-cost single-poly CMOS process flow.

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Section: Introductionmentioning

confidence: 99%

Time Domain Analog Neuromorphic Engine Based on High-Density Non-Volatile Memory in Single-Poly CMOS

2022

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“…With the development of portable electronic products, logic non volatile memory (NVM), fully compatible with the CMOS logic process, is in great demand for various IC modules requiring permanent data storage. [1][2][3][4][5][6][7][8][9] The key features of logic NVM technologies are low-cost, lowvoltage operations, flexibility, and adaptability to different generations of CMOS technologies.…”

Section: Introductionmentioning

confidence: 99%

Differential multiple-time-programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

Hsu

Liao

Chien

et al. 2017

Jpn. J. Appl. Phys.

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In this paper, we present a new differential multiple-time-programmable (MTP) memory cell with a novel slot contact coupling structure in the fin field-effect transistor (FinFET) CMOS process. This MTP cell contains a pair of floating metal gates to store differential data on a single cell. Through differential read operations, the cells are less susceptible to read error caused by cell-to-cell variations. In a nano-scaled FinFET process, the gate dielectric layer becomes too thin to retain charge in the floating gates for long periods of time. Differential cell design further extends the data lifetime, even with the serious charge-loss problem, and reduces the overall intellectual property (IP) area.

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“…Such a technology requires many additional masks and process steps, significantly increasing the price of the tag. In recent years, several Embedded NVM solutions based on a single polysilicon layer have been proposed [4][5][6][7][8], including the ultra-low power consuming C-Flash bitcell [4], developed by Tower Semiconductor Ltd. In this paper, we present a 256-bit C-Flash module, implemented in the TowerJazz core 0.18μm CMOS technology without mask adders.…”

Section: Introductionmentioning

confidence: 99%

A low-cost low-power non-volatile memory for RFID applications

Dagan

Teman

Fish

et al. 2012

2012 IEEE International Symposium on Circuits and Systems

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One of the main obstacles delaying a more widespread use of radio frequency identification (RFID) tags is cost. A critical element of any RFID system is a low power embedded non-volatile memory (NVM) that can be fabricated without additional masks to the core CMOS process. In this paper, we present a 256-bit re-writeable NVM array, implemented in the TowerJazz 0.18μm CMOS process using only standard logic process steps and masks. Based on the single-poly C-Flash bitcell, this array achieves an extremely low static power figure of 3.8μW during operation cycles.

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A 10k-Cycling Reliable 90nm Logic NVM "eCFlash" (Embedded CMOS Flash) Technology

Cited by 7 publications

References 7 publications

Time Domain Analog Neuromorphic Engine Based on High-Density Non-Volatile Memory in Single-Poly CMOS

Time Domain Analog Neuromorphic Engine Based on High-Density Non-Volatile Memory in Single-Poly CMOS

Differential multiple-time-programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

A low-cost low-power non-volatile memory for RFID applications

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