A 10MHz GaN Driver with Gate Ringing Suppression and Active Bootstrap Control

Li, Sheng Teng; Wang, Pin Ying; Chen, Ching Jan; Hsu, Chih-Chao

doi:10.1109/wipdaasia.2019.8760313

Cited by 15 publications

(3 citation statements)

References 3 publications

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“…2. the high di/dt is coupled between the power and the driving loop via the Common Source Inductance LCS. 3. the high dv/dt is coupled to the drive loop through the Miller capacitor CGD [5].…”

Section: Gate Ringingmentioning

confidence: 99%

Gate Ringing Analysis and Driving Circuit Design of GaN HEMT

Fu¹,

Xu²,

Dong³

et al. 2023

J. Phys.: Conf. Ser.

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GaN HEMT can operate at a high switching frequency because of its characteristics, but there are also related problems. This paper analyzes the negative effects of switching oscillations of GaN HEMT, introduces the design criteria of its driving circuit, and analyzes the causes of the Miller effect and gate ringing under the influence of high-frequency parasitic parameters. Then, the corresponding suppression strategies for the above two phenomena are given, and the design of the driving circuit is introduced. Finally, the validity and rationality of the designed driving circuit are verified by experiments.

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Section: Gate Ringingmentioning

confidence: 99%

Gate Ringing Analysis and Driving Circuit Design of GaN HEMT

Fu¹,

Xu²,

Dong³

et al. 2023

J. Phys.: Conf. Ser.

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“…Li, S.T. et al, proposed the theory of active bootstrap control (ABC) [26], that is, the logic control of the high-side signal, low-side signal, and dead time ensures that the bootstrap capacitor is charged only when the low-side power device is turned on. Ke, X. et al, proposed an active BST balancing (ABB) method to achieve bootstrap voltage control [27].…”

Section: Introductionmentioning

confidence: 99%

A Bootstrap Structure Directly Charged by BUS Voltage with Threshold-Based Digital Control for High-Speed Buck Converter

et al. 2021

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This article proposes a high-frequency, area-efficient high-side bootstrap circuit with threshold-based digital control (TBDC) that is directly charged by BUS voltage (DCBV). In the circuit, the voltage of the bootstrap is directly obtained from the BUS voltage instead of the on-chip low dropout regulator (LDO), which is more suitable for a high operating frequency. An area-efficient threshold-based digital control structure is used to detect the bootstrap voltage, thereby effectively preventing bootstrap under-voltage or over-voltage that may result in insufficient driving capability, increased loss, or breakdown of the power device. The design and implementation of the circuit are based on CSMC 0.25 µm 60 V BCD technology, with an overall chip area of 1.4 × 1.3 mm2, of which the bootstrap area is 0.149 mm2 and the figure-of-merit (FOM) is 0.074. The experimental results suggest that the bootstrap circuit can normally operate at 5 MHz with a maximum buck converter efficiency of 83.6%. This work plays a vital role in promoting the development of a wide range of new products and new technologies, such as integrated power supplies, new energy vehicles, and data storage centers.

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“…Shoot-through may also result from ringing in the driving circuit; such phenomenon increases the gate-to-source voltage (V GS ) of the high-side switches above the threshold voltage (V TH ) of the power transistor (Fig. 2(c)) [38]. This issue is commonly observed in gallium nitride (GaN) high electron mobility transistors (HEMTs) because of their low V TH (∼1 V) [39] relative to other types of power switches, such as silicon carbide and conventional silicon (V TH of ∼2.5 V) [40].…”

mentioning

confidence: 99%

An Active Dead-Time Control Circuit With Timing Elements for a 45-V Input 1-MHz Half-Bridge Converter

Karimi

Ali

Hassan

et al. 2022

IEEE Trans. Circuits Syst. I

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In this study, a dead-time control circuit is proposed to generate independent delays for the high and low sides of halfbridge converter switches. In addition to greatly decreasing the losses of power converters, the proposed method mitigates the shoot-through current through the application of superimposed power switches. The circuit presented here comprises a switched capacitor architecture and is implemented in AMS 0.35 µm technology. In the implementation, the proposed dead-time control circuit occupies a silicon area of 70 µm × 180 µm. To realize the technique, a two-sided wide swing current source is employed. Each sides of the current source comes with two capacitors, two Schmitt triggers, and three transmission gates. Results show that the low and high sides of the projected half-bridge converter switches respectively require delays of 35 and 62 ns. The performance of the proposed dead-time circuit is evaluated by assembling it with the half-bridge converter. The proposed dead-time prototype achieves a 40% drop in power losses in the half-bridge circuit.

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A 10MHz GaN Driver with Gate Ringing Suppression and Active Bootstrap Control

Cited by 15 publications

References 3 publications

Gate Ringing Analysis and Driving Circuit Design of GaN HEMT

Gate Ringing Analysis and Driving Circuit Design of GaN HEMT

A Bootstrap Structure Directly Charged by BUS Voltage with Threshold-Based Digital Control for High-Speed Buck Converter

An Active Dead-Time Control Circuit With Timing Elements for a 45-V Input 1-MHz Half-Bridge Converter

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