A 10T, 0.22fJ/Bit/Search Mixed-V<sub><i>T</i></sub>Pseudo Precharge-Free Content Addressable Memory

Datta, Diptesh; Surana, Neelam; Kumar, A. Sanjeev; Mekie, Joycee

doi:10.1109/tcsii.2021.3103880

Cited by 2 publications

(1 citation statement)

References 12 publications

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“…Pre-charge free (PF) [4] [14][18] CAM cell consists of the basic 6T SRAM cell and along with that separate comparison circuit. PF CAM cell uses ten MOSFETs, in that 2 NMOS act as access transistors (N3, N4).…”

Section: Pf Cam Cellmentioning

confidence: 99%

A Novel Design of Low Power, Modified Pre-charge free Binary CAM Array with Pre-computation for Search-Intensive Applications

Gavaskar¹,

Surendar²,

S³

et al. 2022

Preprint

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Memory is a storage space that is essential for storing the repetitive data and the instructions to perform an operation. In modern processors speed has been increased significantly but memory enhancements are mainly focusing on the ability to store more data in less space and to reduce the latency. Content Addressable Memory (CAM) cells are preferred over SRAM cells as they are faster and gives the address of the matched data whereas SRAM uses address to access particular data. The circuit of Modified Pre-charge free CAM cell proposed in this paper is made up of basic 6T SRAM cell (2 cross-coupled inverters and 2 access transistors) and separate comparison circuit (1 PMOS and 1 NMOS transistor). The 8X8 memory array consists of memory cells, row and column decoders, encoder, pre-charge circuits, sense amplifiers and write driver circuits. The various parameters like delay, dynamic power and power delay product are measured and compared with other CAM cells. CADENCE Virtuoso Tool is used for designing the various circuits in 90 nm technology. The simulation results demonstrate that the suggested CAM cell outperforms other cells, hence it is employed to create the array structure. The 8X8 CAM array based on MPF CAM cell has less power and less delay when compared with other array structures.

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Section: Pf Cam Cellmentioning

confidence: 99%

A Novel Design of Low Power, Modified Pre-charge free Binary CAM Array with Pre-computation for Search-Intensive Applications

Gavaskar¹,

Surendar²,

S³

et al. 2022

Preprint

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show abstract

A Segmented Hybrid CAM for High Speed Application Using FinFET

Goswami,

Naidu,

Sameer Basha

et al. 2024

2024 IEEE Region 10 Symposium (TENSYMP)

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A 10T, 0.22fJ/Bit/Search Mixed-V_TPseudo Precharge-Free Content Addressable Memory

Cited by 2 publications

References 12 publications

A Novel Design of Low Power, Modified Pre-charge free Binary CAM Array with Pre-computation for Search-Intensive Applications

A Novel Design of Low Power, Modified Pre-charge free Binary CAM Array with Pre-computation for Search-Intensive Applications

A Segmented Hybrid CAM for High Speed Application Using FinFET

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A 10T, 0.22fJ/Bit/Search Mixed-VTPseudo Precharge-Free Content Addressable Memory

Cited by 2 publications

References 12 publications

A Novel Design of Low Power, Modified Pre-charge free Binary CAM Array with Pre-computation for Search-Intensive Applications

A Novel Design of Low Power, Modified Pre-charge free Binary CAM Array with Pre-computation for Search-Intensive Applications

A Segmented Hybrid CAM for High Speed Application Using FinFET

Contact Info

Product

Resources

About

A 10T, 0.22fJ/Bit/Search Mixed-V_TPseudo Precharge-Free Content Addressable Memory