A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS

Li, Hao; Balamurugan, Ganesh; Jaussi, James; Casper, Bryan

doi:10.1109/esscirc.2018.8494285

Cited by 48 publications

(28 citation statements)

References 3 publications

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“…In Nguyen et al 29 the resistive-feedback configuration was adopted in realizing a programmable gain amplifier. The same idea was exploited in Li et al 43 in distributing the capacitances between subsequent stages, thus extending the bandwidth. In Hong et al 25 a voltage-mode feedforward TIA was proposed to achieve both higher gain and smaller noise figure, however, at the same bandwidth of the conventional inverter-based TIA.…”

Section: Previous Workmentioning

confidence: 94%

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Design of the CMOS inverter‐based amplifier: A quantitative approach

Sharroush

2019

Circuit Theory & Apps

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The CMOS inverter can be used as an amplifier if properly biased in the transition region of its voltage-transfer characteristics (VTC). In this paper, the design of this amplifier is investigated with its merits and demerits illustrated and with the various trade-offs involved in its design discussed. Specifically, the following performance metrics are discussed quantitatively: gain, area, linearity, maximum allowable swing, bandwidth, stability, noise factor, impedance matching, and slew rate. Also, the effect of process, voltage, and temperature (PVT) variations are investigated. The optimum number of stages corresponding to the minimum area required for achieving a certain voltage gain is determined. The results obtained from the quantitative analysis and the simulation are discussed.

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Section: Previous Workmentioning

confidence: 94%

“…22 In Salhi et al 42 it was proposed to connect an inductor in series with the resistor in the feedback path of the inverter-based amplifier as shown in Figure 4E to extend the bandwidth. The same idea was exploited in Li et al 43 in distributing the capacitances between subsequent stages, thus extending the bandwidth.…”

Section: Previous Workmentioning

confidence: 94%

Design of the CMOS inverter‐based amplifier: A quantitative approach

Sharroush

2019

Circuit Theory & Apps

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“…Then, the input-referred noise is obtained by dividing (1) with the trans-impedance gain R as: Nowadays, in order to take advantage of the CMOS inverter in modern process technology, there has been a lot of approaches to adopt CMOS inverter into analog circuits. This paper focuses on the applications of high-speed analog circuits, and introduces three examples of that, amplifier in optical communication receivers [6,[14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30], high-speed clock and data buffer [13,[31][32][33][34][35][36][37][38][39][40][41], and output driver for high-speed I/O transmitter [13,40,[42][43][44][45][46][47][48][49][50].…”

Section: Cmos Inverter As An Amplifiermentioning

confidence: 99%

“…As a result, such inductive feedback leads to a high-frequency peaking, which can be used to compensate the dominant pole by the C PD . Recent state-of-the-arts works in [15,24,29] have combined the series peaking and the inductive feedback, and therefore considerable high-bandwidth at a quite impressive energy efficiency is achieved. Moreover, the authors in [29] saved inductor area by incorporating T-coil inductive peaking.…”

Section: Cmos Inverter As An Amplifiermentioning

confidence: 99%

CMOS Inverter as Analog Circuit: An Overview

Bae

2019

JLPEA

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Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedback inverter, including CMOS inverter as amplifier, high-speed buffer, and output driver for high-speed link, are introduced and discussed in this paper.

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“…The transimpedance amplifier (TIA) typically included in optical receiver designs largely determines the overall sensitivity, operation speed, linearity performance and power consumption of the receiver module [13][14][15][16][17]. A number of optical receivers co-integrated with TIAs have been reported in the literature, the realisations of which were based on various technology platforms, including 250-nm, 130 T [13][14][15][16][17][18][19][20][21][22]. Owing to the higher dynamic range and transition frequency of the BiCMOS technology [23][24], most of the high-speed demonstrations of TIA-integrated optical receivers to date have been realised in BiCMOS processes.…”

Section: Introductionmentioning

confidence: 99%

High-Speed DD Transmission Using a Silicon Receiver Co-Integrated With a 28-nm CMOS Gain-Tunable Fully-Differential TIA

Hong

Lacava

et al. 2021

J. Lightwave Technol.

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We report >100-Gb/s direct-detection (DD) transmission using an integrated silicon optical receiver, which comprised a fully-differential 28-nm complementary metal-oxide-semiconductor (CMOS) transimpedance amplifier (TIA) wire-bonded to a Silicon-Germanium (SiGe) balanced photodiode (PD). The fully-differential TIA architecture enabled significant bit-error-rate (BER) and signal-to-noise ratio improvements over a single-output TIA design when introducing it to the DD transmission. We experimentally validated its effectiveness in both back-to-back (B2B) and 2-km long standard single-mode fibre (SSMF) links using 50/100-Gb/s signals, including Nyquist on-off keying (OOK), Nyquist 4-ary pulse amplitude modulation (PAM4), uniformly-loaded DD optical orthogonal frequency division multiplexing (DDO-OFDM) and adaptively-loaded DDO-OFDM. Furthermore, we demonstrate that the integrated optical receiver was capable of balancing the trade-off between its electrical bandwidth and transimpedance gain by simply adjusting a voltage supply to the TIA. Without the need for optical amplification and while keeping the BERs below the 7% forward error correction limit, up to 173.22-Gb/s and 139.86-Gb/s adaptively-loaded DDO-OFDM transmission was achieved for B2B and 2-km transmission, respectively. The demonstrated results highlight the potential of the integrated silicon optical receiver, fabricated using the standard CMOS process for high-speed and short-reach optical interconnects.

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A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS

Cited by 48 publications

References 3 publications

Design of the CMOS inverter‐based amplifier: A quantitative approach

Design of the CMOS inverter‐based amplifier: A quantitative approach

CMOS Inverter as Analog Circuit: An Overview

High-Speed DD Transmission Using a Silicon Receiver Co-Integrated With a 28-nm CMOS Gain-Tunable Fully-Differential TIA

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