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The nonisothermal melt-crystallization behavior of PA6 and EBA blends at varying EBA content was investigated using differential scanning calorimetry at different scanning rates. Several macrokinetic models such as Avrami, Jeziorny, Ozawa, Liu, Ziabicki, and Tobin were applied to analyze the crystallization behavior thoroughly under nonisothermal conditions. The Avrami and Tobin model predicted that, for pure PA6 and PA6/EBA blends, simultaneous growth of all forms of crystal structures such as fibrillar, disc-like, and spherulitic proceeds at an increasing nucleation rate. However, when applied to blends for isothermal crystallization, the Avrami model predicted that the crystallization process is diffusion-controlled for pure PA6 and PA6/EBA blend containing higher content of EBA (50 phr), where the nylon-6 chains were able to diffuse freely to crystallize under isothermal conditions. Liu model predicted that, at unit crystallization time, a higher cooling rate should be used to obtain a higher degree of crystallinity for both PA6 and PA6/EBA blends. The kinetic crystallizability of PA6 in the blends calculated using Ziabicki's approach varies depending upon the nucleation density and PA6-rich regions present in the blend compositions. Nucleation activity of the blends estimated by Dobreva and Gutzowa method reveals that the EBA particles are inert at lower concentrations of EBA and do not act as nucleating agent for PA6 molecules in the blends. The activation energy of nonisothermal crystallization, calculated using Augis-Bennett, Kissinger, and Takhor methods indicated that the activation energy is slightly lower for the blends when compared to the neat PA6.

This paper describes a new circuit technique for designing noise-tolerant dynamic logic. It is shown that voltage scaling aggravates the crosstalk noise problem and reduces circuit noise immunity, motivating the need for noise-tolerant circuit design. In a 0.35-m CMOS technology and at a given supply voltage, the proposed technique provides an improvement in noise immunity of 1 8 (for an AND gate) and 2 5 (for an adder carry chain) over domino at the same speed. A multiply-accumulate circuit has been designed and fabricated using a 0.35m process to verify this technique. Experimental results indicate that the proposed technique provides a significant improvement in the noise immunity of dynamic circuits (2.4) with only a modest increase in power dissipation (15%) and no loss in throughput.