A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS

Balamurugan, Ganesh; Kennedy, J.; Banerjee, Gaurab; Jaussi, James; Mansuri, M.; O'Mahony, Frank; Casper, Bryan; Mooney, R.

doi:10.1109/jssc.2008.917522

Cited by 129 publications

(57 citation statements)

References 14 publications

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“…The high-speed reference clocks distributed across both the controller and DRAM interfaces. Based on the command traffic from the memory host controller, the appropriate low power states are employed (Leibowitz et al, 2010;Balamurugan et al, 2008;Lee et al, 2009;Poulton et al, 2007).…”

Section: Discussionmentioning

confidence: 99%

“…This operation disables their front-end DQ transceiver circuits, since does not receive any signal transition. The clock pause operation (Balamurugan et al, 2008), responds to programmable number of successive NoOperation (NOP) commands. When the host controller requests a memory transaction, then the interface exits (Lee et al, 2009), synchronously un-pausing the interface clocks.…”

Section: Discussionmentioning

confidence: 99%

“…When the host controller requests a memory transaction, then the interface exits (Lee et al, 2009), synchronously un-pausing the interface clocks. The front-end DQ transceiver circuits (Balamurugan et al, 2008) are initialized to the appropriate read or write configuration after the first CA command is communicated as shown in the Fig. 5.…”

Section: Discussionmentioning

confidence: 99%

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High Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise Reduction

O.¹

2012

Journal of Computer Science

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Problem statement:In any multimedia processor, controller may consume most of the onchip memory resources. The memory requirement is directly depends on algorithm shared by different blocks, so leads to failure in the system models. Approach: This study presents the implementation of DLL unit used for memory optimization. Various aspects of the underlying coarse lock detector are explored and modifications are made with software reference implementation. The whole system is implemented in 0.18 µm CMOS technology, where an input reference clock to an outgoing data clock monitors and true locking is initialized with 50% duty cycle correction. Results: From the measurement result of DLL operation, the output clock jitter is analyzed. Power consumption of DLL including large size output buffer is about few mW. Conclusion: The great challenge in this implementation is communication bandwidth, has brought to process variation and power state reduction techniques. In addition, inefficiency of computing capacity and simultaneous switching noise is reduced in the real time applications.

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Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

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High Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise Reduction

O.¹

2012

Journal of Computer Science

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“…Thus, most source-synchronous architectures use a single global clock in either single-ended or differential form. In each data lane, a DLL or PLL converts the distributed clock into multi-phase clocks one of which is to be picked up for canceling the channel skew and sampling the received data [10,11]. In this architecture, each data lane requires a multiphase generator, a dutycycle corrector and de-skewing circuit.…”

Section: Design Considerationmentioning

confidence: 99%

A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring

Yoo¹,

Song²,

Chi³

et al. 2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A source-synchronous receiver based on a delay-locked loop is presented. It employs a shared global calibration control between channels, yet achieves channel expandability for high aggregate I/O bandwidth.The global calibration control accomplishes skew calibration, equalizer adaptation, and phase lock of all the channels in a calibration period, resulting in the reduced hardware overhead and area of each data lane. In addition, the weightadjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-nm CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9-28 inch Nelco4000-6 microstrips at 4-7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only 0.152 mm 2 and consumes 69.8 mW, while the rest of the receiver occupies 0.297 mm 2 and consumes 56.0 mW at the 7-Gb/s data-rate and supply voltage of 1.35 V.

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“…These include for example ACcoupled pulsed chip-to-chip transceivers [122] and inductive termination to boost transmitted HF components [123]. These also include the capacitive on-chip transmitters that were used in this project [62,124] and in [74,78,121], and with some modifications also in [77].…”

Section: Transmitter-side Equalizationmentioning

confidence: 99%

On-chip data communication : analysis, optimization and circuit design

Schinkel¹

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A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS

Cited by 129 publications

References 14 publications

High Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise Reduction

High Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise Reduction

A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring

On-chip data communication : analysis, optimization and circuit design

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