A 12.08-TOPS/W All-Digital Time-Domain CNN Engine Using Bi-Directional Memory Delay Lines for Energy Efficient Edge Computing

Sayal, Aseem; Nibhanupudi, S. S. Teja; Fathima, Shirin; Kulkarni, Jaydeep P.

doi:10.1109/jssc.2019.2939888

Cited by 55 publications

(20 citation statements)

References 19 publications

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“…In the traditional digital domain of multiplication and addition, large energy consumption of switching capacitors is wasted. Time-domain computing is a method to implement multiplication and addition using the width or delayed superposition of pulses [49][50][51][52]. As shown in Figure 7, a common time-domain calculation consists of two delay lines: reference line and delay line.…”

Section: Cim Architecture Beyond Mixed Solutionmentioning

confidence: 99%

“…Although the time domain is a part of the analog domain, its effective values are only 0 and 1, which can be calculated as a digital domain in nature. Unlike voltage-domain calculations that require large analog-to-digital conversions, the conversion from the time domain to the digital domain can be achieved simply by a counter or a reference line delay detection [49][50][51][52]. The energy-efficient time-domain computing is suitable for low-power AI processors.…”

Section: Cim Architecture Beyond Mixed Solutionmentioning

confidence: 99%

“…It is compatible with multi-bit weighting operations and uses a numerical control oscillator to implement timedomain multiplication and addition. In 2019, Sayal et al [50] proposed a convolutional neural network computational engine for all-digital time-domain computing. A novel bidirectional memory delay line unit is adopted to perform signed accumulation of the input and weighted product, and the conversion from the time domain to the digital domain is achieved using a simple counter.…”

Section: Cim Architecture Beyond Mixed Solutionmentioning

confidence: 99%

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Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

Chang

Zhang

et al. 2021

Sci. China Inf. Sci.

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An artificial intelligence (AI) processor is a promising solution for energy-efficient data processing, including health monitoring and image/voice recognition. However, data movements between compute part and memory induce memory wall and power wall challenges to the conventional computing architecture. Recently, the memory-centric architecture has been revised to solve the data movement issue, where the memory is equipped with the compute-capable memory technique, namely, computing-in-memory (CIM). In this paper, we analyze the requirement of AI algorithms on the data movement and low power requirement of AI processors. In addition, we introduce the story of CIM and implementation methodologies of CIM architecture. Furthermore, we present several novel solutions beyond traditional analog-digital mixed static random-access memory (SRAM)-based CIM architecture. Finally, recent CIM tape-out studies are listed and discussed.

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Section: Cim Architecture Beyond Mixed Solutionmentioning

confidence: 99%

Section: Cim Architecture Beyond Mixed Solutionmentioning

confidence: 99%

Section: Cim Architecture Beyond Mixed Solutionmentioning

confidence: 99%

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Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

Chang

Zhang

et al. 2021

Sci. China Inf. Sci.

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“…TD cores can be implemented using two different architectures, including spatially unrolled (SU) [6], [7], [9] and recursive (REC) [10], [11]. In the SU architecture, inputs and weights are stored in spatially distributed storage elements with a dedicated processing element (PE).…”

Section: Introductionmentioning

confidence: 99%

A Comparative Analysis of Time-Domain and Digital-Domain Hardware Accelerators for Neural Networks

Maharmeh

Sarhan

Hung

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a comprehensive analysis of hardware accelerators for neural networks in both the digital and time domains, where the latter includes spatially unrolled (SU) and recursive (REC) architectures. All accelerators are implemented and synthesized in a 65nm CMOS technology. An identical neural network model is implemented in the digital and time domain for comparative purposes in terms of throughput, power consumption, area, and energy efficiency. Post-synthesis results show that SU achieves the highest energy efficiency of 145 T Op/s/W with a throughput of 4 GOp/s. The digital core is the fastest among other cores, whereas REC is the slowest but is the most area-efficient, occupying 0.114 mm 2 . SU is more suited for applications with stringent power constraints and average performance, while REC is better suited for applications where the area is the most important requirement and the throughput is less significant. In contrast, the digital core is preferable for large neural networks and critical applications that require high performance.

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“…Within the purview of time-based accumulation, pulsewidth [20], [21] and pulse-delay [18], [22], [23] are the two modulation schemes that have been demonstrated onchip. Of these, pulse-(or, event) delay is more promising for MAC applications due to (1) free addition/subtraction in case of delay, and (2) requirement of peripheral pulse re-routing circuitry requirements in the prior.…”

Section: Introductionmentioning

confidence: 99%

Linear Delay-cell Design for Low-energy Delay Multiplication and Accumulation

Shukla¹

2020

Preprint

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A practical deep neural network's (DNN) evaluation involves thousands of multiply-and-accumulate (MAC) operations. To extend DNN's superior inference capabilities to energy constrained devices, architectures and circuits that minimize energy-per-MAC must be developed. In this respect, analog delay-based MAC is advantageous due to reasons both extrinsic and intrinsic to the MAC implementation − (1) lower fixedpoint precision requirement for a DNN's evaluation, (2) better dynamic range than charge-based accumulation, for smaller technology nodes, and (3) simpler analog-digital interfacing. Implementing DNNs using delay-based MAC requires mixedsignal delay multipliers that accept digitally stored weights and analog voltages as arguments. To this end, a novel, linearly tune-able delay-cell is proposed, wherein, the delay is realized using an inverted MOS capacitor's (C * ) steady discharge from a linearly input-voltage dependent initial charge. The cell is analytically modeled, constraints for its functional validity are determined, and jitter-models are developed. Multiple cells with scaled delays, corresponding to each bit of the digital argument, must be cascaded to form the multiplier. To realize such bitwise delay-scaling of the cells, a biasing circuit is proposed that generates sub-threshold gate-voltages to scale C * 's discharging rate, and thus area-expensive transistor width-scaling is avoided. For 130nm CMOS technology, the theoretical constraints and limits on jitter are used to find the optimal design-point and quantify the jitter versus bits-per-multiplier trade-off. Schematiclevel simulations show a worst-case energy-consumption close to the state-of-art, and thus, feasibility of the cell.

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A 12.08-TOPS/W All-Digital Time-Domain CNN Engine Using Bi-Directional Memory Delay Lines for Energy Efficient Edge Computing

Cited by 55 publications

References 19 publications

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

A Comparative Analysis of Time-Domain and Digital-Domain Hardware Accelerators for Neural Networks

Linear Delay-cell Design for Low-energy Delay Multiplication and Accumulation

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