A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation

Nam, Jae-Won; Hassanpourghadi, Mohsen; Zhang, Aoyang; Chen, Mike Shuo-Wei

doi:10.1109/jssc.2018.2808244

Cited by 60 publications

(24 citation statements)

References 12 publications

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“…Further increasing the sampling rate brings in several challenges. First, the time interleaving technique must be utilized which suffers from the matching impairment such as gain-mismatch, offset-mismatch, and time skew [9,10]. Moreover, a large number of interleaved SAR channels is usually inevitable [11,12].…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, a large number of interleaved SAR channels is usually inevitable [11,12]. The calibration circuits increase the design complexity as well as die area, and the adaptability for the on-chip implementation need to be of concern [5,10]. Second, for the SAR ADC with 12 bits resolution, the total sampling capacitance is generally larger than the capacitance considering the thermal noise due to the large number of unit capacitor and its size matching requirement [13].…”

Section: Introductionmentioning

confidence: 99%

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A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS Technology

Guo

Luan

et al. 2020

Electronics

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A 1 GS/s 12-bit pipelined/successive-approximation-register (pipelined/SAR) hybrid analog-to-digital converter (ADC) is presented in this paper, where the five most significant bits are resolved by two cascading 2.5-bit multiplying digital-to-analog converters, and the eight least significant bits are determined by a two-channel time-interleaved successive-approximation-register (TI-SAR) quantizer. An integrated input buffer and an operational amplifier with improved voltage efficiency at 1.8 V are adopted to achieve high-linearity stably in wide band for 1 GS/s. By designing a 500 MS/s 8-bit SAR quantizer at 1 V, the number of required interleaved channels is minimized to simplify the complexity and an adaptive power/ground is used to compensate the common-mode mismatch between the blocks in different power supply voltages. The offset and gain mismatches due to the TI-SAR quantizer are compensated by a calibration scheme based on virtually-interleaved channels. This ADC is fabricated in a 40 nm complementary metal-oxide-semiconductor (CMOS) technology, and it achieves a signal-to-noise-and-distortion ratio (SNDR) of 58.2 dB and a spurious free dynamic range (SFDR) of 72 dB with a 69 MHz input tone. When the input frequency increases to 1814 MHz in the fourth Nyquist zone, it can maintain an SNDR of 55.3 dB and an SFDR of 64 dB. The differential and integral nonlinearities are −0.94/+0.85 least significant bit (LSB) and −3.4/+3.9 LSB, respectively. The core ADC consumes 94 mW, occupies an active area of 0.47 mm × 0.25 mm. The Walden figure of merit reaches 0.14 pJ/step with a Nyquist input.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS Technology

Guo

Luan

et al. 2020

Electronics

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“…In theory, sampling rate can be consistently multiplied along with the increasing channel number. However, the offset mismatch, gain mismatch, and timing mismatch between interleaved channels limit the infinite improvement of the sampling rate, where the timing mismatch is the most difficult one to be calibrated [6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

A Low-Distortion 20 GS/s Four-Channel Time-Interleaved Sample-and-Hold Amplifier in 0.18 μm SiGe BiCMOS

Ding

Zheng

et al. 2019

Electronics

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This paper presents a 20 GS/s four-channel time-interleaved sample-and-hold amplifier (SHA), which aims to improve the harmonic distortion performance, eliminate the common-mode voltage fall in track-to-hold transition, and solve the difficulty of timing mismatch calibration among different sampling channels. In data path, the harmonic distortion of the track-hold switch is optimized by introducing a distortion-improving resistor into the switched emitter follower. The common-mode voltage fall is eliminated by an inserted delay-regulating resistor. Additionally, broadband data buffers are utilized to further guarantee a wide bandwidth. In clock path, an interpolator-based phase regulator in analog domain is implemented to calibrate the timing mismatch, hence avoiding the large area cost and complicated algorithm in the digital domain. Fabricated in a 0.18 μm SiGe BiCMOS process, the experimental results show that the SHA achieves a bandwidth of 16 GHz and a total harmonic distortion of −39.6 to approximately −51.8 dB with a −3 dBm input. By applying the proposed sampling phase regulator, the timing mismatch can be optimized to satisfy the requirement of 6-bit resolution at a 4 × 5 GS/s sampling rate. The proposed SHA shows prominent performance on both bandwidth and linearity, which makes it suitable for ultra-high-speed communication networks.

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“…Based on high performance SAR ADC, time-interleaved SAR ADCs (TI SAR ADC) are superior in aspects of highly scalable and power efficiency to advanced CMOS technology. Several calibration techniques are provided in [23,24,25,26,27,28] to correct the non-ideal errors produced by channel mismatches in time-interleaved SAR ADC. For every type of SAR ADCs, linearity of sampling switch is the bottleneck for system linearity, the parasitic diodes of source/drain to substrate exist in the sampling switch.…”

Section: Introductionmentioning

confidence: 99%

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique

Pu-Jie

et al. 2019

IEICE Electron. Express

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A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique is proposed. With the variation of input signals, the parasitic capacitance variation of sampling switch is reduced and the total parasitic capacitance is also depressed. Moreover, with substrate boost technique, the on-impedance of sampling switch would decrease. To demonstrate the proposed technique, a design of 12bit 100-MS/s SAR ADC is fabricated in 40-nm CMOS technology, consuming 2 mW from 1 V power supply with a SNDR >65 dB and SFDR >83 dB. The proposed ADC core occupies an active area of 0.02 mm 2 , and the corresponding FoM is 13.8 fJ/conversion-step with Nyquist frequency.

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A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation

Cited by 60 publications

References 12 publications

A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS Technology

A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS Technology

A Low-Distortion 20 GS/s Four-Channel Time-Interleaved Sample-and-Hold Amplifier in 0.18 μm SiGe BiCMOS

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique

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