A 12-bit 1-Gword/s GaAs digital-to-analog converter system

Hsieh, Kuo-Chiang; Knotts, Thomas A.; Baldwin, Gary; Hornak, T.

doi:10.1109/jssc.1987.1052854

Cited by 19 publications

(4 citation statements)

References 4 publications

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“…This is because these devices depend on inherently nonlinear devices, switches, which suffer from the speed/accuracy tradeoff Consider the Return-To-Zero (RTZ) sampler shown in Figure 2.14. This struc ture is very similar to the GaAs output device reported by Hsieh [56]. This differential scheme utilizes both the true {lout) &nd complementary {Icomp) DAC currents (in stead of steering the "off" current to ground).…”

Section: Output Samplingsupporting

confidence: 60%

Digital correction of dynamic nonlinearities in digital-to-analog converters

Spalding

George²

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for serving on my committee, to Tom Petersen and IBM, Rochester, MN for funding this research, and to the members of the Video Image Processing Group, Analog Devices Semiconductor, Wilmington, MA, for all their suggestions and assistance. Thanks also to Peter Real, Analog Devices BV, Limerick, Ireland, for having patients when I really needed it, to R.C. Waits of Texas A&M University for providing valuable PC board fabrication and technical assistance, and Roberta "Bert" North for making it all run smoothly.

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Section: Output Samplingsupporting

confidence: 60%

Digital correction of dynamic nonlinearities in digital-to-analog converters

Spalding

George²

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“…Attempts to reduce glitches include the use of latches to synchronize the switch controls, circuits to generate optimal control waveforms for the switches, and the use of return-to-zero-type output to suppress the output during the code changes [232]. The return-to-zero technique utilized in [233] yields a clear improvement in highfrequency SFDR compared to earlier reported DACs, but still has some limitations, such as the difficulty of providing large amplitudes to a low-resistance load, the complicated circuitry needed to handle signal dependent parasitics, and sensitivity to clock jitter, which is not relaxed, unlike in conventional DACs, when signal frequency is decreased.…”

Section: Introduction To Current Steering Dacsmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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“…Calibration, which can remove most DC errors, is not effective against error sources such as glitch and code dependent settling. Instead of correcting these errors, the current approach is to try and minimize them during the circuit design stage [6].…”

Section: Direct Digital Synthesismentioning

confidence: 99%

“…When this new signal passes through the DAC, the output is determined by equation #1 as: (6) Which, to the first order, cancels the distortion. Note that the squaring of the input creates cross products between the fundamental and the correction signal, similar to intermodulation distortion in multi-tone signals.…”

Section: Digital Predistortionmentioning

confidence: 99%

Digital correction for improved spectral response in signal generation systems

Spalding

Geiger

1993 IEEE International Symposium on Circuits and Systems

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A bstract-Signal generation systems using Direct Digital Synthesis (DDS) techniques have received a great deal of attention recently due to their flexibility, repeatability, and wide range of stable operating frequencies. The spectral accuracy of these systems is limited by the analog components used to convert the signal into continuous-time. This work will demonstrate how the addition of digital signal processing and a feedback loop around the analog signal path can increase the spectral quality.

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A 12-bit 1-Gword/s GaAs digital-to-analog converter system

Cited by 19 publications

References 4 publications

Digital correction of dynamic nonlinearities in digital-to-analog converters

Digital correction of dynamic nonlinearities in digital-to-analog converters

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Digital correction for improved spectral response in signal generation systems

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