A 12-bit 10 MS/s 12 mW pipelined SAR ADC for CubeSat systems using <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" display="inline" id="d1e594" altimg="si5.svg"><mml:msub><mml:mrow><mml:mi mathvariant="normal">V</mml:mi></mml:mrow><mml:mrow><mml:mi mathvariant="normal">cm</mml:mi></mml:mrow></mml:msub></mml:math>-based switching MDAC and unit capacitor array

Xue, Feifei; Gao, Wu; Zheng, Ran; Wei, Xiao-Gang; Wang, J.; Hu, Yunlong

doi:10.1016/j.nima.2019.163218

Cited by 3 publications

(1 citation statement)

References 16 publications

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“…The proposed ADC seems to have a suitable performance rather than mentioned pipelined ADCs. Compared to other works, 5,11,20,39,40 the proposed design has higher linearity parameters and input full‐scale range which makes it usable for high precision and widespread electronics applications. Also in comparison to the ADCs that use the digital calibration technique, the proposed calibration‐free ADC has suitable linearity parameters.…”

Section: Simulation Resultsmentioning

confidence: 95%

A low‐power 10‐bit CCP‐based pipelined ADC using a multi‐level variable current source MDAC and an ultra‐low‐power double‐tail dynamic latch

Firouzkouhi

Ashraf

2021

Circuit Theory & Apps

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Summary In this paper, a low‐power 10‐bit 15‐MS/s opamp‐less pipelined analog‐to‐digital converter (ADC) has been proposed. The circuit is comprised of eight 1.5‐bit/stage MDACs and a 2‐bit backend flash ADC. Each 1.5‐bit/stage structure comprises a CCP‐based MDAC which uses a modified multilevel variable‐current‐source (ML‐VCS) scheme. The modified ML‐VCS CCP structure facilitates its usage in a pipeline ADC structure. Also, the proposed ML‐VCS structure improves the speed behavior as well as the power consumption of a 1.5‐bit/stage CCP‐based MDAC structure. In order to further reduce power consumption, an ultra‐low‐power low‐delay double‐tail dynamic latch has been offered which features high‐speed operation. The suggested ADC is simulated using 180‐nm scaled CMOS technology with a 2‐Vp‐p differential full‐scale input voltage. Hspice simulation results show that the ADC exhibits an SNDR of 60‐dB, an ENOB of 9.67 bits, and the FOM of 0.546 PJ/Conv.step at a Nyquist‐rate input frequency. According to the results, the proposed 10‐bit ADC consumes only 6.7‐mW under a 1.8‐V supply voltage.

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Section: Simulation Resultsmentioning

confidence: 95%

A low‐power 10‐bit CCP‐based pipelined ADC using a multi‐level variable current source MDAC and an ultra‐low‐power double‐tail dynamic latch

Firouzkouhi

Ashraf

2021

Circuit Theory & Apps

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Simulation and Performance of Delta Modulator for CubeSat-Based Communications

Casillas-Aviña,

Ramírez-López,

Yáñez-Casas

2024

Communications in Computer and Information Science

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A 5MS/s 12-Bit Successive Approximation Analog-to-Digital Converter

Li,

Cao,

Wang

et al. 2023

OJAppS

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With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.

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A 12-bit 10 MS/s 12 mW pipelined SAR ADC for CubeSat systems using Vcm-based switching MDAC and unit capacitor array

Cited by 3 publications

References 16 publications

A low‐power 10‐bit CCP‐based pipelined ADC using a multi‐level variable current source MDAC and an ultra‐low‐power double‐tail dynamic latch

A low‐power 10‐bit CCP‐based pipelined ADC using a multi‐level variable current source MDAC and an ultra‐low‐power double‐tail dynamic latch

Simulation and Performance of Delta Modulator for CubeSat-Based Communications

A 5MS/s 12-Bit Successive Approximation Analog-to-Digital Converter

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