In this paper, we present a novel data acquisition scheme based on a low-noise front-end readout ASIC and a high speed ADC for PET imaging systems based on cadmium zinc telluride (CZT) detectors. A charge-sensitive amplifier(CSA), a pulse shaper and a driving buffer are integrated for each CZT detector pixel. The specifications of the ASIC are dependent on the dimension of the CZT detector. Eight shaping voltages are sampled and digitized. The data from the ADC is collected by a programmable FPGA which can run an algorithm to calculate the peak value of the shaped voltages and the trigging timing of the shaped pulses. To achieve good noise performances and to realize a flexible front-end electronic system, the front-end ASIC and the ADC are not integrated together. Two ASICs as well as the FPGA chip will be bonded directly on the board. Both the front-end readout chip and the ADC chip are designed in 0.35 μm CMOS processing. The input range of the front-end ASIC is from 2000 e-to 40000 e-. The equivalent noise charge (ENC) is below 200 e-. The shaping time is about 1.5 μs. The simulated results show that the proposed method can achieve good spatial resolution and good detection efficiency, and meanwhile, the time resolution of the PET system is greatly improved.

This paper presents a 12-bit 2 MS/s pipelined successive approximation register (SAR) ADC for CZT-based imaging system. The proposed ADC is divided into a first-stage 6-bit SARbased Multiplying Digital Analog Converter (MDAC) and a second-stage 8-bit SAR ADC. The first-stage MDAC has a gain of 16 instead of the usual gain of 64, which considerably minimizes the power dissipation of residue amplifier. The second-stage 8-bit SAR ADC employs unit bridge capacitor split-capacitor architecture aiming to reduce the load capacitance of residue amplifier so as to minimize the power dissipation of the proposed ADC. Moreover, a code-randomized calibration algorithm is proposed to improve the linearity of the second-stage 8-bit split-capacitor SAR ADC. In addition, several radiation-hardened-by-design techniques are adopted in the layout design against space radiation effects. The prototype chip was fabricated in 0.18 µm mixed-signal 1.8 V/3.3 V process and occupied a core area of 0.71 mm 2 . The proposed pipelined SAR ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 63.2 dB at 2 MS/s sampling rate and consumes 12 mW power in total. The figure of merit (FoM) of the proposed ADC is 5.06 pJ/conversion-step. K: Data acquisition circuits; Front-end electronics for detector readout; Radiation damage to electronic components 1Corresponding author.

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