A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching

Liu, Shubin; Shen, Yi; Zhu, Zhangming

doi:10.1109/tcsi.2016.2581177

Cited by 98 publications

(35 citation statements)

References 31 publications

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“…With a near 1.5 MHz input frequency, the prototype ADC achieves an SFDR of 65.2 dB and SNDR of 57.4 dB, yielding a FoM of 35.4 fJ/conversion-step. The overall performance of the prototype ADC is summarized in Table 2 and compared to references [14][15][16][17]. Figure 11 shows the signal to noise and distortion ratio (SNDR) performance of prototype SAR ADC according to the delay codes.…”

Section: Cal Code @ 25mmentioning

confidence: 99%

A 13-bit 3-MS/s Asynchronous SAR ADC with a Passive Resistor Based Loop Delay Circuit

Lee

2019

Electronics

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An asynchronous successive approximation register (SAR) ADC incorporates a passive resistor based delay cell to reduce power consumption and accommodate the SAR ADC with a reconfigurable sampling frequency or tapered bit period without repeated delay calibration. The ADC aims to have a sampling frequency of several MS/s. The proposed delay cell adopts resistance controlled delay architecture to generate a delay of nanoseconds with high linearity. The resistance controlled delay cell is based on a passive resistor instead of a MOS transistor using a triode region to avoid the nonlinear delay characteristic of active devices. From the analysis of the linearity of delay cell, the passive resistor based delay cell achieves a delay error of about 5 percent. The prototype ADC to validate the proposed passive resistor based delay cell is fabricated in 40 nm CMOS. The ADC occupies 0.054 mm2 and achieves an SNDR of 57.4 dB under 67 μW power dissipation at a 1.1 V supply with a 3 MHz sampling frequency.

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Section: Cal Code @ 25mmentioning

confidence: 99%

A 13-bit 3-MS/s Asynchronous SAR ADC with a Passive Resistor Based Loop Delay Circuit

Lee

2019

Electronics

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“…1(a). The proposed single-ended SAR ADC uses an asynchronous architecture to increase the sampling rate without increasing the frequency of the external clock, compared with a typical SAR ADC [16][17][18][19][20][21][22]. The binary search operation of the SAR logic, shown in Fig.…”

Section: Proposed Single-ended Asynchronous Sar With Cdac Boosting Comentioning

confidence: 99%

A 10-bit 10-MS/s single-ended asynchronous SAR ADC with CDAC boosting common-mode voltage and controlling input voltage range

Son

Jang

2019

IEICE Electron. Express

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A capacitor digital-to-analog converter (CDAC), which boosts the common-mode voltage and controls the input voltage rang, is proposed to improve the dynamic range and linearity of a singleended successive approximation register (SAR) analog-to-digital converter (ADC). The 10-bit 10-MS/s single-ended asynchronous SAR ADC using the proposed CDAC is implemented by using a 180-nm CMOS process with a supply voltage of 1.8 V. Its active area and power consumption are 0.207 mm 2 and 2.29 mW, respectively. The measured DNL and INL are +0.93/−0.51 LSBs and +0.61/−0.81 LSBs, respectively. The measured ENOB is 9.04 bits for the analog input signal with Nyquist frequency.

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“…Figure 4(1) shows a capacitor array of the first part, which we cannot make sure the voltage distribution on its bottom plates. Turn off S5 and all the switches between the bottom plates and the reference voltage, and short the MSB and LSB respectively [8]. Then, the MSB is changed to V cm while the LSB is changed to Gnd.…”

Section: Reset Energymentioning

confidence: 99%

Two-step switching scheme for SAR ADC with high energy efficiency

Zhang

Liu

Zhu

2018

Analog Integr Circ Sig Process

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The paper presents two high energy-efficiency switching schemes for the successive approximation register (SAR) analogue-to-digital converter (ADC). The first scheme is a part of the second one. The new switching schemes achieves no switching energy consumption in the first three comparison, and need no reset energy. Thus, compared with the conventional SAR architecture, 99.23 and 99.42% reduction in switching energy is achieved respectively. Moreover, the total scheme achieves an 86.7% reduction in unit capacitor number by its special architecture.

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A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching

Cited by 98 publications

References 31 publications

A 13-bit 3-MS/s Asynchronous SAR ADC with a Passive Resistor Based Loop Delay Circuit

A 13-bit 3-MS/s Asynchronous SAR ADC with a Passive Resistor Based Loop Delay Circuit

A 10-bit 10-MS/s single-ended asynchronous SAR ADC with CDAC boosting common-mode voltage and controlling input voltage range

Two-step switching scheme for SAR ADC with high energy efficiency

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