A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters

Tseng, Wei-Hsin; Lee, Wei‐Liang; Huang, Changyang; Chiu, Pao-Cheng

doi:10.1109/jssc.2016.2582861

Cited by 74 publications

(28 citation statements)

References 12 publications

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“…The mismatch between the buffers is calibrated only once at start-up and the additional hardware required is just an adder/subtractor. Table 1 shows a benchmark of our buffered ADC and the buffered ADCs in [1] and [6]. Note that most of the energy efficient SAR ADCs do not include input buffers which limits the scope of the comparison.…”

Section: Measurement Resultsmentioning

confidence: 99%

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A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply

Bindra

Annema

Wienk

et al. 2019

2019 IEEE Custom Integrated Circuits Conference (CICC)

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We present a 10b differential SAR ADC integrated with unity gain (Class-A) voltage buffers, operating from a single supply voltage 1.2V and handling near rail-to-rail inputs. The two differential inputs are first compared and depending on the comparison result, the inputs are either swapped or not, after which these signals are buffered, sampled and converted. This way each of the two buffers needs to handle only half of the full-scale range which enables operation of the Class-A buffers at the ADC supply voltage while providing an overall near rail-to-rail (fullscale) input range for conversion. The buffered ADC can handle 2VP-P differential input and consumes 149µW at 4MS/s to achieve a state-of-the-art Walden FoM of 87fJ/conversion-step including buffers. The buffered ADC was designed in a 65nm CMOS process and occupies an active area of 0.04mm 2 .

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Section: Measurement Resultsmentioning

confidence: 99%

“…Simulations show that Q IN,MAX is 30fC per sample operation for each channel, of which 18fC is delivered to the input of the buffer, 7fC to the FE comparator and 5fC to the switches in SWP1. # Calculated for the ENOB near Nyquist B/W as per the measurement data in [6] instead of at low frequency as reported in [6].…”

Section: Introductionmentioning

confidence: 99%

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply

Bindra

Annema

Wienk

et al. 2019

2019 IEEE Custom Integrated Circuits Conference (CICC)

View full text Add to dashboard Cite

show abstract

“…In recent years, with the improvement of CMOS technology, successive approximation register (SAR) analog-todigital converters ADCs have been able to achieve sampling rates of several hundreds of MS/s with high power efficiency and small area [1,2,3,4,5,6,7,8,9,10]. Meanwhile, 8 to 12-bit SAR ADCs could reach sampling rates of hundreds or thousands MS/s and provide compact area and outstanding power efficiency [11,12,13,14,15,16,17,18,19,20,21,22]. Based on high performance SAR ADC, time-interleaved SAR ADCs (TI SAR ADC) are superior in aspects of highly scalable and power efficiency to advanced CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique

Pu-Jie

et al. 2019

IEICE Electron. Express

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A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique is proposed. With the variation of input signals, the parasitic capacitance variation of sampling switch is reduced and the total parasitic capacitance is also depressed. Moreover, with substrate boost technique, the on-impedance of sampling switch would decrease. To demonstrate the proposed technique, a design of 12bit 100-MS/s SAR ADC is fabricated in 40-nm CMOS technology, consuming 2 mW from 1 V power supply with a SNDR >65 dB and SFDR >83 dB. The proposed ADC core occupies an active area of 0.02 mm 2 , and the corresponding FoM is 13.8 fJ/conversion-step with Nyquist frequency.

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“…High SNDR ADCs are widely used in mixed-signal system-on-chip (SoC) in the fields of both the industrial and the consumer applications. The SAR ADC is well known as a high energy efficiency ADC architecture for medium resolution, low or medium speed applications [1,2,3,4,5,6,7]. However, because the resolution of SAR ADC depends on the offset of comparator and the accuracy of capacitor array matching, it is difficult to realize the high resolution ADC in nanoscale CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

Experimental implementation of delta sigma AD modulator using dynamic analog components with simplified operation phase

Pan

San

2019

IEICE Electron. Express

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A proof-of-concept delta sigma AD modulator using dynamic analog components with simplified operation mode is designed and fabricated in 90 nm CMOS technology. The measurement results of the experimental prototype demonstrate the feasibility of the proposed modulator architecture which can guarantee the reset time for ring-amplifier and relax the speed requirement on the asynchronous SAR quantizer. The peak SNDR of 77.93 dB and SNR of 84.16 dB are achieved while a sinusoid −4 dBFS input is sampled at 14 MS/s with signal bandwidth of 109 kHz. The total analog power consumption of the prototype modulator is 720 µW under the supply voltage of 1.2 V.

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A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters

Cited by 74 publications

References 12 publications

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique

Experimental implementation of delta sigma AD modulator using dynamic analog components with simplified operation phase

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