A 12 bit 200 MHz low glitch CMOS D/A converter

Solving Static and Dynamic Performance Limitations for High Speed D/A Converters

“…Until a few years ago, open literature used to mention mainly static specifications of D/A converters [1,2]. Recent publications [3,4,5] have revealed that a combination of a high update rate, a high …”

Design techniques for high-performance current-steering digital-to-analog converters

“…Many strategies have been reported in the literature to solve these problems. For example, latches are placed right in front of the switches to reduce the timing skew and improve the synchronization [12]- [14],[l7], [19], [23]- [37], [49], [50]; switch drivers are used to avoid the two switches being turned off simultaneously and hence reduce the voltage fluctuation at the common node of the switches [12], [13], [17], [19], [23]- [37], [49], [50]; Cascode transistors can be added between the switches and the output to reduce the clock feedthrough through the gate-drain capacitance of the switches [13], [15]; A cascode transistor can also be added between the current source and the switches to reduce glitch due to the drain voltage variation of the current source [18].…”

“…Other methods for gradient error compensation include providing well-established local biasing for each quadrant of the current matrix [5], [35], splitting each current source into several units located symmetrically in the matrix [12], [13], [19], [23]- [25] and etc. These methods effectively suppress the spatial gradient errors and the linearity of the DACs are thus determined by the residual errors in the local region, which can be further compensated with either the row-column switching scheme or the "random walk" scheme.…”

“…This potential has been seen in many current-steering DAC designs [5], [12]- [14], [17], [19], [23]- [25], [27]. [28], [46]- [49].…”

“…In a current-steering DAC, the switching scheme determines the interconnection between the outputs of the thermometer decoder/latch and the control terminals of the switches in the current matrix. As an example, an 8-bit thermometer decoded current-steering DAC is shown in Several switching schemes and sequences have been heuristically derived in literature for gradient error compensation in unary arrays of DACs [5], [12], [14], [17], [19], [23]- [25], [27], [28], [46], [49], However, no real analytical treatment has been attempted to verify whether these switching schemes and sequences are sufficient to compensate for the gradient errors and the issue whether better solutions exist has not been addressed. A general approach is necessary to find optimal or near optimal switching sequences under any given type of gradient condition.…”