A 12 bit 250 MS/s 28 mW +70 dB SFDR non-50% RZ DAC in 0.11 µm CMOS using controllable RZ window for wireless SoC integration

Kim, Seonggeon; Kang, Ji-Hoon; Lee, Minjae

doi:10.1016/j.mejo.2016.08.005

Cited by 4 publications

(1 citation statement)

References 20 publications

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“…Thus, selection of resistor value is important to eliminate the issue (Esmaili and Babazadeh, 2019b). Chou and Hung (2016) stated that current steering architecture has advantages of speed and linearity but higher power consumption (Kim et al , 2016) and glitch (Lai et al , 2019). Combining two of these architectures results a new architecture namely hybrid DAC, which has the most advantages and the least disadvantages (Rahman et al , 2017; Rosli et al , 2019).…”

Section: Introductionmentioning

confidence: 99%

A 1.8 V high-speed 8-bit hybrid DAC with integrated rail-to-rail buffer amplifier in CMOS 180 nm

Idros

Rosli

Aziz

et al. 2021

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Purpose The purpose of this paper is to present the performance of an 8-bit hybrid DAC which is suitable for wireless application or part of a built-in test block for ADC. The hybrid architecture used is the combination of thermometer coding and binary-weighted resistor architectures. Design/methodology/approach The conventional DAC topology performance tends to degrade at high-resolution applications. A hybrid topology, which combines an equal number of bits of thermometer coding and binary-weighted resistor architectures operating at higher sampling frequency, was proposed in this work. The die was fabricated in 180 nm CMOS process technology with a supplied voltage of 1.8 V. Findings Measured results showed that the DNL and INL errors are within −1 to +1 LSB and −0.9 to +0.9 LSB, respectively for the input range of 0.9 V at the clock rate of 200 MHz, and this DAC was proven monotonic. This 0.068 mm2 DAC consumed 12.6 mW for the data conversion. Originality/value This paper is of value in showing the equal division of bits from thermometer coding and binary-weighted resistor architectures provides smaller die size and enhances the performance of hybrid DAC, in terms of linearity, which are DNL and INL errors and guarantees monotonicity at higher sampling frequency.

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Section: Introductionmentioning

confidence: 99%

A 1.8 V high-speed 8-bit hybrid DAC with integrated rail-to-rail buffer amplifier in CMOS 180 nm

Idros

Rosli

Aziz

et al. 2021

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A 16-bit DPT-DAC over 120dBc SFDR with Signal-Phase regulation and Switching-Glitch neutralization

Dong,

Yang,

et al. 2024

AEU - International Journal of Electronics and Communications

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Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS

2019

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In this paper, very compact, standard cell-based Digital-to-Analog converters (DACs) based on the Dyadic Digital Pulse Modulation (DDPM) are presented. As fundamental contribution, an optimal sampling condition is analytically derived to enhance DDPM conversion with inherent suppression of spurious harmonics. Operation under such optimal condition is experimentally demonstrated to assure resolution up to 16 bits, with 9.4-239X area reduction compared to prior art. The digital nature of the circuits also allows extremely low design effort in the order of 10 man-hours, portability across CMOS generations, and operation at the lowest supply voltage reported to date. The limitations of DDPM converters, the benefits of the optimal sampling condition and digital calibration were explored through the optimized design and the experimental characterization of two DACs with moderate and high resolution. The first is a general-purpose DAC for baseband signals achieving 12-bit (11.6 ENOB) resolution at 110kS/s sample rate and consuming 50.8µW, the second is a DAC for DC calibration achieving 16-bit resolution with 3.1-LSB INL, 2.5-LSB DNL, 45µW power, at only 530µm 2 area.INDEX TERMS Digital to analog converter (DAC), automated design, calibration, fully synthesizable, fully digital, ultra-low design effort, standard-cell-based analog circuits.

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A 12 bit 250 MS/s 28 mW +70 dB SFDR non-50% RZ DAC in 0.11 µm CMOS using controllable RZ window for wireless SoC integration

Cited by 4 publications

References 20 publications

A 1.8 V high-speed 8-bit hybrid DAC with integrated rail-to-rail buffer amplifier in CMOS 180 nm

A 1.8 V high-speed 8-bit hybrid DAC with integrated rail-to-rail buffer amplifier in CMOS 180 nm

A 16-bit DPT-DAC over 120dBc SFDR with Signal-Phase regulation and Switching-Glitch neutralization

Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS

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