2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)
DOI: 10.1109/iscas.2004.1328133
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A 12-bit 40MSPS 3.3-V 56-mW pipelined A/D convereter in 0.25-μm CMOS [convereter read converter]

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(2 citation statements)
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“…Even though the lower gain of the optimal OTA introduces larger static errors (with respect to the folded topology), the gain bandwidth product is larger and allows closed loop performances compatible with digital correction. The optimal platform instance includes a digital corrector simpler than in (11), but still able to compensate within LSB/2 the distortion levels introduced by the SHA.…”
Section: Resultsmentioning
confidence: 99%
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“…Even though the lower gain of the optimal OTA introduces larger static errors (with respect to the folded topology), the gain bandwidth product is larger and allows closed loop performances compatible with digital correction. The optimal platform instance includes a digital corrector simpler than in (11), but still able to compensate within LSB/2 the distortion levels introduced by the SHA.…”
Section: Resultsmentioning
confidence: 99%
“…Furthermore, digital calibration techniques improve overall flexibility and design yield. Compared to traditional pipelined ADC optimization approaches [8][9][10][11][12][13], which mainly focus on analytical models used to determine performance of single stage blocks, we exploit accurate simulation-based performance models that consider important effects as Sample-and-Hold Amplifier (SHA) distortion, charge injection and, finally, the impact of digital calibration. This approach allows avoiding expensive design iterations caused by non feasibility of performance requirements at the bottom level of abstraction resulting from the inaccurate architectural modeling used in standard top-down flows.…”
Section: Introductionmentioning
confidence: 99%