A 12 bit 8 GS/s Time-Interleaved SAR ADC in 28nm CMOS

Linnhoff, Sebastian; Buballa, Frowin; Reinhold, Michael; Gerfers, Friedel

doi:10.1109/icecs49266.2020.9294903

Cited by 7 publications

(3 citation statements)

References 7 publications

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“…The FE-buffer is depicted in Fig. 3a, where a pseudodifferential push-pull architecture with bootstrapped drain nodes is used [1], [6], [10]. With this architecture, the FEbuffer output resistance is minimized.…”

Section: Circuit Designmentioning

confidence: 99%

A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI

Wittenhagen

Artz

Scholz

et al. 2022

IEEE Open J. Solid-State Circuits Soc.

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In this article, a 3 GS/s Time-Interleaved (TI) RF Track-and-Hold (TaH) amplifier designed in a 22 nm SOI technology is presented. The TaH amplifier is designed to drive an ADC, which can be either two pipeline-ADCs or two rows of SAR-ADCs. Both TI TaH are driven by a single RF-matched wide-band bulk-controlled Front-End (FE) buffer. The measured TaH amplifier has a SFDR beyond 70 dBc up to 2.5 GHz and remains above 67 dBc till 3 GHz enabling sub-sampling. An overall system bandwidth of 4.5 GHz is achieved with a SNR above 55 dBFS. The ultra-low-jitter clock regeneration has only 45 fs rms jitter not limiting the SNR up to 3 GHz. Two-tone and multi-tone measurements reveal a third intermodulation and inter-band non-linearity with >72 dBFS and >82 dBFS respectively. Off-chip calibration of offset/gain mismatch and time-skew between both TaH-lanes reduce interleaving spurs >75 dBFS utilizing a 37-tap fractional delay FIR filter. The efficient body-bias control of the technology is used to dynamically body-bias the TaH sample-switch increasing bandwidth by 10% improving settling performance while at the same time the leakage decreases. Static body-biasing is also applied to the common-mode-feedback by using the bulk as an control node. The TaH amplifier including the clock generation consumes only 178 mW from a triple 2 V/0.9 V/-0.8 V supply.

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Section: Circuit Designmentioning

confidence: 99%

A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI

Wittenhagen

Artz

Scholz

et al. 2022

IEEE Open J. Solid-State Circuits Soc.

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“…A fourth sub-buffer is used to drive a single reference-ADC. All buffers are implemented in a pseudo-differential push-pull architecture, to achieve a high linearity, while maintaining a good power efficiency [2]. The overall system clock, applied to all sub-ADCs, operates at 8 GHz.…”

Section: Overall Adc Architecturementioning

confidence: 99%

A 12 Bit 500 MS/s Sub-2 Radix SAR ADC for a Time-Interleaved 8 GS/s ADC in 28 nm CMOS

Buballa

Linnhoff

Reinhold

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…This method has high complexity and high hardware costs, which are not suitable for practical applications. References [19][20][21] studied the correction structure of reference channel randomization. Since the requirement for noise is lower than that for harmonic or spurious, the reference channel randomization structure is an expedient scheme based on this principle.…”

Section: Introductionmentioning

confidence: 99%

Error Correction Method of TIADC System Based on Parameter Estimation of Identification Model

Sun

Zhang

et al. 2022

Applied Sciences

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The performance of analog-to-digital converters (ADCs) has reached a bottleneck due to the limitations of the manufacturing process and testing environment. Time-interleaved ADC (TIADC) technology can increase the sampling rate without changing the resolution. However, channel mismatch severely degrades the dynamic performance of the TIADC system. For the channel mismatch problem of TIADC, most of the current solutions have preconditions, such as eliminating only some kind of error or increasing the complexity of the hardware. A few methods can estimate multiple errors without changing the hardware circuit. To improve the dynamic performance of the TIADC system, on the basis of an in-depth study of the channel mismatch error of TIADC, according to the system identification theory, an identification model is designed to characterize the frequency characteristics of TIADC. Using the system observation data, the transfer function parameters of the system are recursively estimated. By constructing and verifying the identification model of the TIADC system, and then through the frequency domain correction method, a digital compensation filter is established to complete the error correction of the system. The test results of the four-channel TIADC high-speed data acquisition system show that the actual input and output characteristics of the test system are consistent with the nature of the identification model. The four channels of the TIADC system are provided by four sub-channels of two AD9653 chips, and the highest sampling rate of a single channel is 125MSPS. For sinusoidal input signals from 20 MHz to 150 MHz, the sampling system can achieve a signal-to-noise ratio (SNR) above 56.8 dB and spurious free dynamic range (SFDR) above 69.7 dB. The dynamic performance of the sampling system is nearly equivalent to that of its sub-ADC; the feasibility of the model identification method and the effectiveness of error correction are verified in simulation and experiment.

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A 12 bit 8 GS/s Time-Interleaved SAR ADC in 28nm CMOS

Cited by 7 publications

References 7 publications

A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI

A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI

A 12 Bit 500 MS/s Sub-2 Radix SAR ADC for a Time-Interleaved 8 GS/s ADC in 28 nm CMOS

Error Correction Method of TIADC System Based on Parameter Estimation of Identification Model

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