No abstract

This paper presents a wideband 12 Bit 8 GS/s timeinterleaved successive approximation register (SAR) analog-todigital converter (ADC), featuring a sub-2 radix architecture with an overrange of 10% and randomized sampling with mismatch correction in a 28 nm CMOS technology. For this purpose, 18 500 MHz SAR-ADCs plus an additional reference ADC are interleaved. This topology enables a randomization approach, reducing mismatch related interleaving spurs. Furthermore, the additional reference ADC operating in parallel to the main ADC enables adaptive digital calibration to correct for static and time-interleaved mismatch effects. A wideband front-end features two subsequent push-pull buffer stages to achieve a high trackand-hold (T/H) bandwidth and high sampling linearity, while improving kickback related settling limitations. After calibration, the ADC achieves a signal to noise and distortion ratio (SNDR) of 56.8 dB and a spurious free dynamic range (SFDR) of 80 dBc applying a single full scale sine wave tone close to the Nyquist frequency of 4 GHz.

No abstract

No abstract

No abstract