A 12 Bit 8 GS/s Randomly-Time-Interleaved SAR ADC with Adaptive Mismatch Correction

Linnhoff, Sebastian; Sippel, Erik; Buballa, Frowin; Reinhold, Michael; Vossiek, Martin; Gerfers, Friedel

doi:10.1109/iscas51556.2021.9401579

Cited by 2 publications

(2 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, gm1 must be set by the input frequency and operation speed of the T/H. Since the T/H circuit was measured with a signal frequency input, H3(jωa, jωb, jωc), which relates to 3 rd -order distortion, can be expressed as (8) under the condition ωa=ωb=ωc=ω1. Subsequently, using (5) to (8), the ratio of the 3 rd -order distortion to the fundamental tone (HD3) can be expressed as in ( 9)…”

Section: A Track-mode Distortionmentioning

confidence: 99%

An Active Track and Hold Circuit With Linearity Enhancement Technique and Its Analysis Using Volterra Series

Jang,

Lee,

Kim

2024

IEEE Access

View full text Add to dashboard Cite

This paper presents a comprehensive analysis of active track and hold (T/H) circuits that utilize switched source followers and time-divided post-distortion cancellation. In the track phase, the circuit acts as an active buffer and transfers an input signal, including track-mode distortion caused by the buffer's nonlinear transconductance. In the hold phase, the transferred signal is held but hold-mode distortion is added, including hold-mode feed-through and hold pedestal error, causing deterioration of the circuit's linearity. The timedivided post-distortion cancellation technique improves the circuit's linearity by cancelling the track-mode distortion with the hold-mode distortion. Volterra series analysis offers a comprehensive understanding of the operation. 17 sample chips were measured to verify stable cancellation operation. It shows a mean SFDR value of 77.1 dB and a standard deviation of 1.8 dB with 9mW power consumption.

show abstract

Section: A Track-mode Distortionmentioning

confidence: 99%

An Active Track and Hold Circuit With Linearity Enhancement Technique and Its Analysis Using Volterra Series

Jang,

Lee,

Kim

2024

IEEE Access

View full text Add to dashboard Cite

show abstract

“…This method has high complexity and high hardware costs, which are not suitable for practical applications. References [19][20][21] studied the correction structure of reference channel randomization. Since the requirement for noise is lower than that for harmonic or spurious, the reference channel randomization structure is an expedient scheme based on this principle.…”

Section: Introductionmentioning

confidence: 99%

Error Correction Method of TIADC System Based on Parameter Estimation of Identification Model

Sun

Zhang

et al. 2022

Applied Sciences

View full text Add to dashboard Cite

The performance of analog-to-digital converters (ADCs) has reached a bottleneck due to the limitations of the manufacturing process and testing environment. Time-interleaved ADC (TIADC) technology can increase the sampling rate without changing the resolution. However, channel mismatch severely degrades the dynamic performance of the TIADC system. For the channel mismatch problem of TIADC, most of the current solutions have preconditions, such as eliminating only some kind of error or increasing the complexity of the hardware. A few methods can estimate multiple errors without changing the hardware circuit. To improve the dynamic performance of the TIADC system, on the basis of an in-depth study of the channel mismatch error of TIADC, according to the system identification theory, an identification model is designed to characterize the frequency characteristics of TIADC. Using the system observation data, the transfer function parameters of the system are recursively estimated. By constructing and verifying the identification model of the TIADC system, and then through the frequency domain correction method, a digital compensation filter is established to complete the error correction of the system. The test results of the four-channel TIADC high-speed data acquisition system show that the actual input and output characteristics of the test system are consistent with the nature of the identification model. The four channels of the TIADC system are provided by four sub-channels of two AD9653 chips, and the highest sampling rate of a single channel is 125MSPS. For sinusoidal input signals from 20 MHz to 150 MHz, the sampling system can achieve a signal-to-noise ratio (SNR) above 56.8 dB and spurious free dynamic range (SFDR) above 69.7 dB. The dynamic performance of the sampling system is nearly equivalent to that of its sub-ADC; the feasibility of the model identification method and the effectiveness of error correction are verified in simulation and experiment.

show abstract

A 12 Bit 8 GS/s Randomly-Time-Interleaved SAR ADC with Adaptive Mismatch Correction

Cited by 2 publications

References 9 publications

An Active Track and Hold Circuit With Linearity Enhancement Technique and Its Analysis Using Volterra Series

An Active Track and Hold Circuit With Linearity Enhancement Technique and Its Analysis Using Volterra Series

Error Correction Method of TIADC System Based on Parameter Estimation of Identification Model

Contact Info

Product

Resources

About