A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors

Abstract

This paper proposes a novel 12-bit column-parallel two-step single-slope (SS) analog-todigital converter (ADC) for high-speed CMOS image sensors. Cooperating with the output offset storage (OOS) technique, a new correlated double sampling (CDS) is adopted to reduce the non-uniformity in column-level ADCs. In the proposed structure, the decision point of the comparator is independent of the input signal. The variation of the comparator offset caused by the input level is eliminated. Through a foreground calibration, the non-idealities from the ramp generator and the column ADC are both corrected. Design and simulation in a 130nm CMOS process, the proposed ADC achieves the differential nonlinearity (DNL) of +0.76/-0.8 LSB and the integral nonlinearity (INL) of +1.06/-0.84 LSB at a sampling frequency of 100 KS/s with the calibration. The effective number of bits (ENOB) is also improved from 4.66 bits to 11.25 bits. The single ADC occupies an active area of 7.5×775 μm 2 and the power consumption is 72 μW. INDEX TERMS Column-parallel ADC; single-slope (SS) ADC; two-step ADC; foreground calibration

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

“…Due to the advanced technology and system architecture of the ADC designed in this paper, the actual speed improvement is basically consistent with the theoretical analysis. It can be observed that the design method proposed in this paper has obvious advantages compared with the existing references [ 6 , 7 , 8 , 9 ].…”

“…The ADC architectures in the table are all compared under the accuracy of 12-bit. References [ 6 , 7 , 8 ] are all two-step structures with coarse and fine conversion. Compared with [ 6 ], the power consumption of the proposed design is reduced by 14% and the conversion speed is improved by 95.2%.…”

“…References [ 6 , 7 , 8 ] are all two-step structures with coarse and fine conversion. Compared with [ 6 ], the power consumption of the proposed design is reduced by 14% and the conversion speed is improved by 95.2%. Compared with [ 7 ], the power consumption of the proposed design is reduced by 45% and the conversion speed is improved by 92.5%.…”

“…In recent years, the research on ADC applied to the CIS field involved a large number of different ADC topologies, such as successive approximation ADC (SAR ADC) [ 1 ], σ-δ ADC [ 2 ], cyclic ADC (Cyclic ADC) [ 3 ], flash ADC (Flash ADC), pipeline ADC (Pipeline ADC) [ 4 ], single-slope ADC (SS-ADC) [ 5 ], and various combinations of the aforementioned ADC architectures. Considering the trade-off between speed, power consumption, and area, not every ADC structure is suitable for CIS [ 6 , 7 , 8 , 9 , 10 ].…”