A 12-bit integrated analog front-end for broadband wireline networks

Mehr, I.; Maulik, P.; Paterson, D.

doi:10.1109/cicc.2001.929737

Cited by 7 publications

(3 citation statements)

References 4 publications

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“…It indicates that the PGA needs to have smaller than 74-dB total harmonic distortion (THD) over the signal spectrum, and amplifies the received signal by 0 to 20-dB gain control range [2], [3]. Signal attenuation may be required to accommodate large input signal swing [4]. The PGA needs to maintain its high linearity and low noise over the entire signal bandwidth as well as gain range.…”

Section: Introductionmentioning

confidence: 99%

A highly linear 125-mhz cmos switched-resistor programmable-gain amplifier

Hsu

2003

IEEE J. Solid-State Circuits

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A highly linear programmable-gain amplifier (PGA) is fabricated using a 0.35-m CMOS technology. High linearity and constant wide bandwidth are achieved by using a high-gain amplifier with low input impedance and resistor-network feedback. The voltage gain is varied by digitally controlling the input switched resistors. The distortion of a switched resistor has been analyzed using the Volterra series. The PGA has a voltage gain varying from 0 to 19 dB, while maintaining a constant bandwidth of 125 MHz. The third-order intermodulation distortion is 86 dB at 10 MHz. The circuit dissipates 21 mW from a 3.3-V supply.

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Section: Introductionmentioning

confidence: 99%

A highly linear 125-mhz cmos switched-resistor programmable-gain amplifier

Hsu

2003

IEEE J. Solid-State Circuits

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“…A ring-oscillator-based PLL is implemented with <70ps rms jitter. A layout is depicted in Figure 19 Compared to state-of-the-art designs in 0.35µm CMOS with similar performance, [5,6] this AFE surpasses the others in die size by a factor of more than 2. This can be attributed partially to the implementation in a smaller feature size CMOS process and in the choice of the ADC.…”

Section: Infineon Technologies Ag Villach Austriamentioning

confidence: 99%

A 1.8V 450mW VDSL 4-band analog front end IC in 0.18μm CMOS

Weinberger

Wiesbauer²,

Clara³

et al.

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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VDSL transceivers exploit an extremely high analog bandwidth. Therefore VDSL modems can achieve bit-rates to 52Mb/s. The required analog input dynamic range is approximately 90dB. For standard 4-band VDSL, 12MHz bandwidth is required, comprising two up-stream and two down-stream signals as depicted in Figure 19.4.1. A robust digital modulation technique (single carrier QAM) keeps linearity requirements moderate compared to other DSL modems. Harmonic distortion components up to -55dBc can be tolerated.A chipset consisting of a 4-band digital datapump (VDSL-D) and a highly-integrated analog front-end (AFE) chip provide a complete solution for standard 4-band VDSL. The AFE uses a 0.18µm CMOS process and single 1.8V supplies. All receiver and transmitter functionality is included in a single chip, as depicted in the functional block diagram of Figure 19.4.2. The receiver dynamic range requirement is achieved by a 32dB programmable gain amplifier (PGA) followed by an 11b ADC. The pre-filter (PREFI) removes high-frequency signals which would cause aliasing in ADC sampling. For partial compensation of line attenuation at high frequencies, an analog channel equalizer (ACE) is used. The transmit function is provided by the 12b DAC, a reconstruction filter (POFI), and a programmable-gain amplifier (POCO). On-chip clock is generated with a digitallycontrolled crystal oscillator and a PLL. The AFE uses fully-differential circuits.The wake up circuit consists of an analog filter and a comparator, converting QAM modulated bursts to a digital signal, followed by a digital bit sequence detector. Since wake up is sensitive to a predefined sequence of "1" and "0", robust detection of a wakeup signal is guaranteed.The PGA consists of 2 gain stages providing up to 32dB gain in total. Each stage is based on a Miller op-amp with resistive feedback, providing 2Vpp signal swing with harmonic distortion <-60dBc and input referred noise <-140dBm/Hz. It is advantageous to use an analog channel equalizer in the receive channel. A first-order filter with up to 9dB gain at frequencies above 2MHz is implemented.Both PREFI and POFI are 3 rd -order Chebyshev filters of op-amp RC type. As described in [1], the filter corner frequency is tuned automatically to ±5%. The corner frequency is programmable between 8MHz and 12MHz to allow optimum configuration for use in central office or remote terminal.Candidates for the ADC are pipeline, subranging flash, and sigma-delta ADCs. Today, sigma-delta ADCs do not achieve VDSL performance in terms of resolution and bandwidth. They are feasible for ADSL [2] but not yet available for more than 2MHz bandwidth. Pipeline ADCs fit the performance requirements, although they typically require several square millimeters silicon area and rather high supply currents [3]. Subranging Flash ADCs are typically limited to 9-10b accuracy, due to the matching properties of the CMOS processes [4]. But they can be operated with sampling rates in excess of 100MHz, consuming moderate power and moderate silicon area. This design...

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“…In signal processing and telecommunication systems, the digital-to-analog converters (DACs) are used to reconstruct the analog signal from arbitrary digital waveform. DACs are a key part which limits the accuracy and speed of the overall system [2] [3]. The DACs can be generally divided into two main types according to the sampling frequency to input signal ratio: Nyquist-rate converters and oversampling converters [4].…”

Section: Chapter 2 Dac Architecture Nonlinearities and Calibrationmentioning

confidence: 99%

Dynamic calibration of current-steering DAC

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A 12-bit integrated analog front-end for broadband wireline networks

Cited by 7 publications

References 4 publications

A highly linear 125-mhz cmos switched-resistor programmable-gain amplifier

A highly linear 125-mhz cmos switched-resistor programmable-gain amplifier

A 1.8V 450mW VDSL 4-band analog front end IC in 0.18μm CMOS

Dynamic calibration of current-steering DAC

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