A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS

Kim, Dongwook; Ahmed, Mostafa Gamal; Choi, Woo-Seok; Elkholy, Ahmed; Hanumolu, Pavan Kumar

doi:10.1109/jssc.2020.2978138

Cited by 18 publications

(6 citation statements)

References 22 publications

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“…The work of [8] concentrates on both timing and output DC-level recovery simultaneously and takes 58 UIs for the lock. This work achieves a faster lock time and a comparable power dissipation to [11] implemented in the same technology. The proposed work incorporates ILOs.…”

Section: Comparison and Conclusionmentioning

confidence: 96%

“…Recent works on burst-mode solutions for optical networks, wireline electrical, and vertical-cavity surfaceemitting laser (VCSEL)-based optical transceivers have been presented in [5]- [11]. In [6], power-hungry limiting amplifiers (LAs) are replaced with a variable-gain amplifier (VGA) to improve the energy efficiency during the active state.…”

Section: Introductionmentioning

confidence: 99%

“…Both the settling of the dc-level and the CDR locking take place simultaneously in [8] to reduce the overall turn-on time. The CDR of [11] uses an area-intensive architecture that sweeps the oscillator phase after each idle period to achieve a phase match with the data signal for the lock, resulting in a long recovery time. However, all of the solutions discussed above address the turn-on time for a single-channel burst-mode receiver.…”

Section: Introductionmentioning

confidence: 99%

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Fast-Locking Burst-Mode Clock and Data Recovery for Parallel VCSEL-Based Optical Link Receivers

Abbas

Cowan

2022

IEEE Access

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A burst-mode clock-and-data-recovery (CDR) system for a multi-channel vertical-cavity surface-emitting laser (VCSEL)-based non-return-to-zero (NRZ) optical link's quarter-rate receivers is presented, that utilizes proxy timing recovery for fast turn-on time. The proxy timing recovery scheme takes advantage of correlated data jitter over parallel optical lanes typically deployed in a data center. Rapid timing recovery of the burst-mode channel is enabled by incrementing/decrementing its phase rotator (PR) control code during idle periods using phase updates from an always-active channel in the link. This work also presents circuit-design techniques to reduce power dissipation during idle times while still enabling fast turnon time. Simulated in 65 nm CMOS technology, the proposed CDR consumes only 19.5 mW per channel while operating at 10 Gbps/ch and 0.58 mW during its idle-state. Simulation results are presented for the turn-on time with the proposed technique and compared against the turn-on time of a conventional receiver. The proposed technique allows the CDR to lock within 26 unit intervals (UIs) from when it is powered on irrespective of a 1000 ppm frequency offset between the incoming data and the CDR's reference clock. The complete CDR of each channel occupies an area of 0.045 mm 2 . The proposed scheme introduces only 1.3 % of area and 2.6 % of on-state power overhead while reducing idle-time power dissipation by 97 %.INDEX TERMS Burst-mode, clock and data recovery (CDR), energy efficiency, injection locked oscillator (ILO), optical link, power-proportional, transimpedance amplifier (TIA).

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Section: Comparison and Conclusionmentioning

confidence: 96%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Fast-Locking Burst-Mode Clock and Data Recovery for Parallel VCSEL-Based Optical Link Receivers

Abbas

Cowan

2022

IEEE Access

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“…In contrast to conventional systems, the overall power consumption of the proposed one is no longer directly proportional to the total number of sensors but rather proportional to the occurrence of events of interest. For such contextaware systems, since communication between the readout IC and the processor is required only when events occur, communication link I/Os need to support rapid turning on/off operation for overall system energy proportionality [17]- [19].…”

Section: Proposed Tsp Readout Systemmentioning

confidence: 99%

A Context-Aware Readout System for Sparse Touch Sensing Array Using Ultra-low-power Always-on Event Detection

Roh¹,

Choi²

2022

Preprint

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Increasing demand for larger touch screen panels (TSPs) places more energy burden to mobile systems with conventional sensing methods. To mitigate this problem, taking advantage of the touch event sparsity, this paper proposes a novel TSP readout system that can obtain huge energy saving by turning off the readout circuits when none of the sensors are activated. To this end, a novel ultra-low-power always-on event and region of interest detection based on lightweight compressed sensing is proposed. Exploiting the proposed event detector, the context-aware TSP readout system, which can improve the energy efficiency by up to 40×, is presented.

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“…Common equalization techniques in high-speed serial links can be divided into liner equalizers (LE) and decision feedback equalizer (DFE) [5,6,7,8,9]. LE uses the frequency characteristics of the adjustable filter to compensate the channel loss, but for high-speed (> 5 Gbps) serial link, since the signal jitter (such as ISI related deterministic jitter) may exceed a symbol interval (UI), using LE alone is no longer applicable [10,11,12,13].…”

Section: Introductionmentioning

confidence: 99%

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

Zhu

Chu

2023

IEICE Electron. Express

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This work proposes a RX front-end structure, which is used for channel equalization of 25 Gb/s high-speed links. This design includes two parts, linear equalizer and decision feedback equalizer. Linear equalizer consists of the variable gain amplifier, the continuous-time linear equalizer and the output buffer, which provide 19 dB peaking gain around the Nyquist frequency. The half-rate decision feedback equalizer with one speculative tap is cascaded after the buffer to eliminate residual inter-symbol interference. The circuit layout occupies an area of 0.005 mm 2 designed in 65 nm CMOS, the power consumption of which is 96 mW under 1.2 V power supply. The design is used to equalize the FR-4 backplane channel, of which the insertion loss reaches 35 dB at 12.5 GHz. The result shows that both the voltage margin and time margin of the receiver signal reach 171 mV and 0.61 UI at the BER of 10 −12 , respectively.

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A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS

Cited by 18 publications

References 22 publications

Fast-Locking Burst-Mode Clock and Data Recovery for Parallel VCSEL-Based Optical Link Receivers

Fast-Locking Burst-Mode Clock and Data Recovery for Parallel VCSEL-Based Optical Link Receivers

A Context-Aware Readout System for Sparse Touch Sensing Array Using Ultra-low-power Always-on Event Detection

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

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