A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF

Chae, Hyungil; Jeong, Jae−Hun; Manganaro, Gabriele; Flynn, Michael P.

doi:10.1109/jssc.2013.2291713

Cited by 53 publications

(27 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To put the results in context, the work is compared with recently reported FF-compensated amplifiers of bandpass Σ∆ modulators in Table II. The amplifiers in [1], [4], [6] were designed to work in Σ∆ modulators at f s = 0.8 GHz, 0.8 GHz and 1 GHz respectively. This work achieves the highest unitygain-frequency at 11 GHz.…”

Section: Results and Comparisonmentioning

confidence: 99%

“…This work achieves the highest unitygain-frequency at 11 GHz. It consumes 13 and 21 mW more than [4] and [6] respectively. However, it improves the gain at 2 GHz by 12 dB compared to [6] and by 17 dB with respect to that of [4].…”

Section: Results and Comparisonmentioning

confidence: 99%

“…It consumes 13 and 21 mW more than [4] and [6] respectively. However, it improves the gain at 2 GHz by 12 dB compared to [6] and by 17 dB with respect to that of [4]. Compared to [1], this work improves the gain performance at both 1 GHz…”

Section: Results and Comparisonmentioning

confidence: 99%

“…However, it achieves it with a supply voltage of 2.5 V in its input and output stages. Reference [4] implements a four-stage two-path amplifier and incorporates Nested Millercompensation to improve its phase margin (PM). It relies on a 1.25 V supply and achieves a DC gain of 80 dB.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Design of a 4th-Order Feed-Forward-Compensated Operational Amplifier for Multi-GHz Sampling Frequency Continuous-Time Bandpass Sigma-Delta Modulators

Gebreyohannes¹,

Louërat²,

Aboushady³

2019

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

This work presents a 4 th-order multi-stage, multipath, feed-forward-compensated operational amplifier in 65 nm CMOS technology. It is designed to meet the requirements of a continuous-time bandpass Σ∆ modulator with multi-GHz sampling frequency. The designed amplifier is modular with each stage implemented based on a unit differential amplifier block and it meets its targets with smart placement of poles and zeros. The amplifier is simulated under the loading condition of a single-amplifier resonator which is in turn part of a 6 thorder Σ∆ modulator. The unloaded amplifier reaches a unitygain-frequency of 38.29 GHz and a DC gain of 58 dB. With a parallel load of 440 fF and 300 Ω, representing the maximum load, the op-amp, including common-mode and biasing circuits, consumes a total of 18.98 mA from a supply voltage of 1.2 V. It is unconditionally stable with a phase margin of 54 • and has gains of 35 dB and 23 dB at 1 GHz and 2 GHz respectively.

show abstract

Section: Results and Comparisonmentioning

confidence: 99%

Section: Results and Comparisonmentioning

confidence: 99%

Section: Results and Comparisonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design of a 4th-Order Feed-Forward-Compensated Operational Amplifier for Multi-GHz Sampling Frequency Continuous-Time Bandpass Sigma-Delta Modulators

Gebreyohannes¹,

Louërat²,

Aboushady³

2019

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

show abstract

“…The main difference between the proposed MRZ waveform and the conventional RZ and halfdelayed RZ (HRZ) [15,21,22] waveforms is in the jitter effect of the clock, which is employed to produce these DAC pulses. In the generation of the RZ and HRZ pulses, the two edges of the DAC pulse in a pulse period are affected, independently from each other, by the random fluctuations of the clock edges.…”

Section: Proposed Technique In Design Of the Dac Pulse For Clock-jittmentioning

confidence: 99%

A single‐bit continuous‐time delta‐sigma modulator using clock‐jitter and inter‐symbol‐interference suppression technique

Sabouhi

Aghdam

Saeedi

2016

Circuit Theory & Apps

View full text Add to dashboard Cite

SUMMARYThis paper presents a technique for mitigating two well-known DAC non-idealities in continuous-time delta-sigma modulators (CTDSMs), particularly in wide-band and low over-sampling-ratio (OSR) cases. This technique employs a special digital-to-analog convertor (DAC) waveform, called modified returnto-zero (MRZ), to reduce the time uncertainty effect because of the jittered clock at the sampling time instances and eliminate the effect of inter-symbol-interference (ISI) which degrades the modulator performance, especially when non-return-to-zero (NRZ) DAC waveform is chosen in the modulator design. A third-order single-bit CTDSM is designed based on the proposed technique and step-by-step design procedure at circuit and system levels, considering clock jitter and ISI, is explained. Circuit simulations in 180-nm CMOS technology show that in the presence of circuit non-idealities which generate jitter and asymmetrical rise and fall times in the DAC current pulse, signal-to-noise-distortion-ratio (SNDR) of the proposed modulator is higher than the conventional modulator with NRZ waveform by about 10 dB. In these simulations, clock jitter standard deviation is 0.3% of the sampling period (T S ) and the difference between fall/rise times in the DAC current pulse is 4%T S . Simulated at 600-MHz sampling frequency (f S ) with an oversampling ratio (OSR) of 24, SNDR figure of merit (FOM SNDR ) of the proposed modulator in 180-nm CMOS is 300 fj/conversion.

show abstract

Frontiers, Trends and Challenges: Towards Next‐generation ΣΔ Modulators

Rosa¹

2018

Sigma‐Delta Converters

View full text Add to dashboard Cite

A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF

Cited by 53 publications

References 20 publications

Design of a 4th-Order Feed-Forward-Compensated Operational Amplifier for Multi-GHz Sampling Frequency Continuous-Time Bandpass Sigma-Delta Modulators

Design of a 4th-Order Feed-Forward-Compensated Operational Amplifier for Multi-GHz Sampling Frequency Continuous-Time Bandpass Sigma-Delta Modulators

A single‐bit continuous‐time delta‐sigma modulator using clock‐jitter and inter‐symbol‐interference suppression technique

Frontiers, Trends and Challenges: Towards Next‐generation ΣΔ Modulators

Contact Info

Product

Resources

About