A 120 GS/s 2:1 Analog Multiplexer with High Linearity in SiGe-BiCMOS Technology

A 200-Gb/s 70-GHz-bandwidth 2:1 analog multiplexer in 130-nm SiGe BiCMOS process

“…Although the ADCs and DACs using SiGe and InP processes realized higher sampling rate and wider BW [5,6,7,8], they are not compatible with CMOS-based DSPs. In response to these challenges, previous studies have recently started developing analog multiplexers (AMUXs) [1,9,10,11,12,13,14,15,16] and analog demultiplexers (ADEMUXs) [17,18,19,20,21,22,23,24,25], which simultaneously achieved high data rate and compatibility between ADCs/DACs and DSPs. In this paper, a 2:1 AMUX in IHP's 130-nm SiGe BiCMOS process is introuduced.…”

160-GSa/s-and-Beyond 108-GHz-Bandwidth Over-2-Vppd Output-Swing 0.5-μm InP DHBT 2:1 AMUX-Driver for Next-Generation Optical Communications

“…2(a)]. Such architecture is used in [3], [11], and [15], whereas, in [12]- [14], two Gilbert cells are actively combined through a cascode amplifier. Because, in this last architecture, four differential pairs must be simultaneously driven by the clock signal, it implies higher routing complexity and higher footprint and imposes more stringent clock-alignment requirements, compared to single-Gilbertcell AMUX designs, for a given technology.…”