A 125μW, fully scalable MPEG-2 and H.264/AVC video decoder for mobile applications

Liu, Tsu-Ming; Lin, Tsung-Nan; Wang, Sheng-Zen; Lee, Wen-Ping; Hou, Kang-Cheng; Yang, Jiun-Yan; Lee, Chen‐Yi

doi:10.1109/isscc.2006.1696212

Cited by 21 publications

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

Cache Optimization for H.264/AVC Motion Compensation

Yoon

Chae

2008

IEICE Transactions on Information and Systems

View full text Add to dashboard Cite

SUMMARYIn this letter, we propose a cache organization that substantially reduces the memory bandwidth of motion compensation (MC) in the H.264/AVC decoders. To reduce duplicated memory accesses to P and B pictures, we employ a four-way set-associative cache in which its index bits are composed of horizontal and vertical address bits of the frame buffer and each line stores an 8 × 2 pixel data in the reference frames. Moreover, we alleviate the data fragmentation problem by selecting its line size that equals the minimum access size of the DDR SDRAM. The bandwidth of the optimized cache averaged over five QCIF IBBP image sequences requires only 129% of the essential bandwidth of an H.264/AVC MC.

show abstract

Cache Optimization for H.264/AVC Motion Compensation

Yoon

Chae

2008

IEICE Transactions on Information and Systems

View full text Add to dashboard Cite

show abstract

A 439K gates/10.9KB SRAM/2–328 mW dual mode video decoder supporting temporal/spatial scalable video

Chien

Yang

Chang

et al. 2009

2009 IEEE Asian Solid-State Circuits Conference

View full text Add to dashboard Cite

The first dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width is proposed. A design automation environment of simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 μm CMOS technology, it comprises 439Kgates/10.9KB SRAM and consumes 2~328mW in decoding CIF~HD1080 videos at 3.75~30fps when operating at 1~150MHz, respectively.

show abstract

A 658KGates e-streaming video decoder for digital home applications

Chen

Lin

Liu

et al. 2009

2009 IEEE Asian Solid-State Circuits Conference

View full text Add to dashboard Cite

The first reported RealVideo-embedded video decoder is presented The embedded streaming (e-Streaming) video decoder integrates RealVideo, MPEG-2, MPEG-4, H.264, and VC-1 by 658K logic gates and 522Kbits SRAM. In particular, a RealVideo (RV) is fully-reused and is first integrated into our multi-standard video decoder [1]. It explores RV temporal reference method , RV VLD table reduction, multi-stage pipeline and memory management unit to facilitate cost and bandwidth efficiency for digital home and internet services. The test chip is fabricated and the first using 55nm CMOS process which occupies 658KGates/522Kbits SRAM on 1.56x1.56mm 2 die and dissipates 195mW in full HD@30fps RV playback.

show abstract

A 125μW, fully scalable MPEG-2 and H.264/AVC video decoder for mobile applications

Cited by 21 publications

References 19 publications

Cache Optimization for H.264/AVC Motion Compensation

Cache Optimization for H.264/AVC Motion Compensation

A 439K gates/10.9KB SRAM/2–328 mW dual mode video decoder supporting temporal/spatial scalable video

A 658KGates e-streaming video decoder for digital home applications

Contact Info

Product

Resources

About

A 125μW, fully scalable MPEG-2 and H.264/AVC video decoder for mobile applications

Cited by 21 publications

References 19 publications

Cache Optimization for H.264/AVC Motion Compensation

Cache Optimization for H.264/AVC Motion Compensation

A 439K gates/10.9KB SRAM/2&#x2013;328 mW dual mode video decoder supporting temporal/spatial scalable video

A 658KGates e-streaming video decoder for digital home applications

Contact Info

Product

Resources

About

A 439K gates/10.9KB SRAM/2–328 mW dual mode video decoder supporting temporal/spatial scalable video