A 12b 1.25GS/s DAC in 90nm CMOS with &amp;#x003E;70dB SFDR up to 500MHz

Tseng, Wei-Hsin; Fan, Chi-Wei; Wu, Jieh-Tsorng

doi:10.1109/isscc.2011.5746278

Cited by 15 publications

(5 citation statements)

References 4 publications

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“…As an example, the DAC in [15], implemented in CMOS 0.18 µm process, presents 60 dBc SFDR with output current of 30 mA at sampling frequency of 1.4 GSps. In a 90 nm CMOS technology node and half of the previous output current (16 mA), the DAC in [16] exhibits SFDR of 67 dBc at very close sampling rate (1.25 GSps). Doubling the SFDR in this case is a result of dividing the current by a factor of two and the major gain of the technology is to reduce the power and area by factor of three in addition to more complex and faster digital control section.…”

Section: Discussionmentioning

confidence: 99%

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SFDR considerations for current steering high-speed digital to analog converters

Khafaji

Scheytt

Jorges

et al. 2012

2012 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

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In this paper the spurious free dynamic range (SFDR) of a current steering digital-to-analog converter (DAC) is related to the process parameters used for its implementation. It is shown that the realization of such DACs in advanced processes provides power and area reduction combined with faster signaling. However, it is very challenging to improve the SFDR at a certain given output swing and sampling frequency. It is demonstrated that the SFDR can be doubled by using an optimized cascode switch. It is also concluded that compared to MOSFET based approaches higher sampling frequencies can be achieved by bipolar transistor based DACs if the SFDR and transition frequency are fixed. The reason is the higher Early voltage of bipolar transistors.

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Section: Discussionmentioning

confidence: 99%

“…Bipolar cascode (16) where β is the current gain of the BJT cascode transistor. The transconductance and the output resistance for MOSFET cascode are denoted by g m,cas and R o,cas , respectively.…”

Section: B Cascode Switchmentioning

confidence: 99%

SFDR considerations for current steering high-speed digital to analog converters

Khafaji

Scheytt

Jorges

et al. 2012

2012 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

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“…Timing circuits are needed to synchronize data, but at a cost of higher power consumption and area. The digital blocks in our analysis are mainly implemented with CMOS static logic [11]- [13], but it is noted that current-mode logic (CML) is also utilized in high-speed DACs [14]. It is wellknown that digital power consumption equals [15]…”

Section: Digital Domainmentioning

confidence: 99%

Analysis of energy consumption bounds in CMOS current-steering digital-to-analog converters

Chacon

Wikner

Svensson

et al. 2022

Analog Integr Circ Sig Process

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In this paper, an attempt to estimate energy consumption bounds versus signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) in CMOS current-steering digital-to-analog converters is presented. A theoretical analysis is derived, including the design corners for noise, speed and linearity for the mixed-signal domain. The study is validated by comparing the theoretical results with published measured data. As result it serves as a design reference to aim for minimum energy consumption. It is found that for an equivalent number of bits (ENOBs), the noise-bound grows at a rate of 22ENOB, whereas the speed-bound increases by 2ENOB−2 and is dependent on device dimensions. Therefore, as the technology scales down, the noise bound will dominate, which is observed for an estimated SNR of about 40 dB in 65 nm CMOS process. The linearity bound is derived from an analysis based on the assumption of limited output impedance, where it is found to be dependent on the device dimensions and increase at a rate of 2ENOB−1. The observations show that it is possible to achieve less energy consumption in all the design corners for different SNR and SFDR specifications within the Nyquist frequency, fs/2.

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“…But these methods won't improve higher frequency performance since matching isn't the limiting factor any longer. Return to zero (RZ) method is used in [3], [4] to improve high-frequency performance, but this will lose half of the signal power thus limits its application fields. The purpose of this paper is to design a DAC which can get better SFDR at high-frequency without RZ method.…”

Section: Introductionmentioning

confidence: 99%

A 14-bit 2-GS/s DAC with SFDR>70dB up to 1-GHz in 65-nm CMOS

Zhao

et al. 2011

2011 9th IEEE International Conference on ASIC

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a 14-bit 2-GS/s 5-5-4 segmented current-steering digital-to-analog converter is presented in this paper. To improve the high frequency performance, a "fast switching" technique which adds additional biasing to the current-switch is adopted. Also data dependent clock loading effect is minimized with better switch control and double latch method. Post-layout simulation shows that this DAC maintains 70-dB SFDR over Nyquist frequency band up to 2-GS/s and dissipates a power of 82 m W while driving a 50 n load with an output swing of 2.5V pp"The chip is designed in 65nm CMOS technology and has an active area of 0.9 mm 2 • I.

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A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz

Cited by 15 publications

References 4 publications

SFDR considerations for current steering high-speed digital to analog converters

SFDR considerations for current steering high-speed digital to analog converters

Analysis of energy consumption bounds in CMOS current-steering digital-to-analog converters

A 14-bit 2-GS/s DAC with SFDR>70dB up to 1-GHz in 65-nm CMOS

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A 12b 1.25GS/s DAC in 90nm CMOS with &#x003E;70dB SFDR up to 500MHz

Cited by 15 publications

References 4 publications

SFDR considerations for current steering high-speed digital to analog converters

SFDR considerations for current steering high-speed digital to analog converters

Analysis of energy consumption bounds in CMOS current-steering digital-to-analog converters

A 14-bit 2-GS/s DAC with SFDR&#x003E;70dB up to 1-GHz in 65-nm CMOS

Contact Info

Product

Resources

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A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz

A 14-bit 2-GS/s DAC with SFDR>70dB up to 1-GHz in 65-nm CMOS