2020
DOI: 10.1109/jssc.2020.3020194
|View full text |Cite
|
Sign up to set email alerts
|

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1

Citation Types

0
27
0
1

Year Published

2022
2022
2024
2024

Publication Types

Select...
6
2

Relationship

0
8

Authors

Journals

citations
Cited by 72 publications
(28 citation statements)
references
References 28 publications
0
27
0
1
Order By: Relevance
“…However, a conventional single-stage FIA can only achieve a very modest DC gain (less than 20–30 dB). The two-stage FIA realized in [ 19 , 20 ] increases the DC gain at the cost of incurring an increased input-referred noise. In this paper, a cascoded FIA is used as the integrator in - ADC to improve the DC gain while not affecting the noise.…”
Section: Readout Circuitmentioning
confidence: 99%
See 1 more Smart Citation
“…However, a conventional single-stage FIA can only achieve a very modest DC gain (less than 20–30 dB). The two-stage FIA realized in [ 19 , 20 ] increases the DC gain at the cost of incurring an increased input-referred noise. In this paper, a cascoded FIA is used as the integrator in - ADC to improve the DC gain while not affecting the noise.…”
Section: Readout Circuitmentioning
confidence: 99%
“…During the amplification phase (integrate phase ), the cascoded inverters are powered by and amplify the input signal. The charge stored in becomes depleted as current flows through the circuit, and hence, finally, the inverters shut off [ 20 ]. The integrator using only one stage dynamic amplifier circuit does not need a common mode feedback circuit, nor does it have the problem of stability.…”
Section: Readout Circuitmentioning
confidence: 99%
“…The power consumption of this implementation is negligible as well. As for the area overhead, a recent developed ΔΣ ADC [12] in 65 nm CMOS occupies 0.04 mm 2 , and the one [10] in 40 nm CMOS occupies 0.037 mm 2 . Compared with the area of an entire PLL, for example, 0.56 mm 2 [6], the area overhead of the proposed architecture does not take a large portion.…”
Section: Proposed Mash2‐k Fdc‐pllmentioning
confidence: 99%
“…The ADC can be implemented employing dynamic amplifiers and/or with a successive approximation register (SAR) topology [9][10][11][12]. These circuits, based on switched capacitors and switched transistors, have been proven to be friendly to scaled process technology.…”
mentioning
confidence: 99%
“…The function of noise coupling (NC) added to a conventional ADC helps to improve the randomness of the cryptoristor. Unlike efforts to remove residual voltage in a conventional ADC, the side effect of residual voltage, typically having a negative connotation, is positively used as the NC effect (30,31). Kim et al (20) demonstrated a circuit-based tRNG using residual voltage in an ADC.…”
Section: Introductionmentioning
confidence: 99%