A 13.5-mW 5-GHz Frequency Synthesizer With Dynamic-Logic Frequency Divider

Pellerano, Stefano; Levantino, Salvatore; Samori, Carlo; Lacaita, A.L.

doi:10.1109/jssc.2003.821784

Cited by 185 publications

(113 citation statements)

References 15 publications

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“…It is required a rail-to-rail input to work properly. Moreover, at these frequencies, the power consumptions are lowest compared with the SCL logic (Pellerano et al, 2004). The ratios of 30 and 31 were achieved with the use of frequency dividers by 2/3 with modulus control.…”

Section: Frequency Synthesizermentioning

confidence: 98%

A 2.4 GHZ Wireless Electronic Shirt for Vital Signals Monitoring

Carmo

Mendes²,

Couto³

et al. 2008

Proceedings of the First International Conference on Biomedical Electronics and Devices

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Abstract:This paper presents a wireless sensor network for wireless electronic shirts. This allows the monitoring of individual biomedical data, such as the cardio-respiratory function. The solution chosen to transmit the body's measured signals for further processing was the use of a wireless link, working at the 2.4 GHz ISM band. A radio-frequency (RF) CMOS transceiver chip was designed in the UMC RF 0.18 μm CMOS process. The power supply of the RF CMOS transceiver is of only 1.5 V, thus it can be supplied by a single coin-sized battery. The receiver has a sensibility of -60 dBm and consumes 6.2 mW. The transmitter delivers an output power of 0 dBm with a power consumption of 15.6 mW. Innovative topics concerning efficient power management was taken into account during the design of the RF CMOS transceiver.

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Section: Frequency Synthesizermentioning

confidence: 98%

A 2.4 GHZ Wireless Electronic Shirt for Vital Signals Monitoring

Carmo

Mendes²,

Couto³

et al. 2008

Proceedings of the First International Conference on Biomedical Electronics and Devices

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“…The speed of the prescaler can benefit from the decreasing of propagation delay of t 2 . Compared to the reported TSPC 2/3 prescaler [3,4,5,6,7,8], the proposed 2/3 prescaler contains the least number of transistors, and the number of the latches is reduced from 6 to 5 stages.…”

Section: Dual-modulus Prescalermentioning

confidence: 99%

“…With the improved speed of the MOS devices, in several GHz applications, the current-mode-logic (CML) divider can be replaced with the true single-phase clocked (TSPC) logic to reduce the power consumption. Several TSPC prescaler topologies have been proposed to offer high speed and low power [3,4,5,6,7]. In [5] a dual-modulus divide-by-2/3 prescaler exploiting the forced-discharging method in the second branch of a TSPC flip-flop, can substantially improves the maximum speed of the standalone prescaler.…”

Section: Introductionmentioning

confidence: 99%

A 2.4 GHz fractional-N PLL with a low-power true single-phase clock prescaler

Xia

Wang

et al. 2017

IEICE Electron. Express

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A 2.4 GHz fractional-N PLL implemented in 65-nm CMOS process is presented in this letter. A TSPC dual-modulus prescaler is proposed to reduce the PLL's power consumption by merging one of the branches of the true single-phase clocked (TSPC) D flip-flops. The measured synthesizer output frequency ranges from 2.16 to 2.7 GHz, and consumes 8 mW from a 1.3 V power supply. The in-band phase noise is −98 dBc/Hz at 100 kHz offset, and −115 dBc/Hz at 1 MHz offset at a carrier frequency of 2.438 GHz. The circuit achieves the RMS jitter of 0.86 ps and figure of merit of −230 dB, with the fractional spurs below −55 dBc.

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“…A bandwidth of approximately twice the difference between the maximum and minimum frequencies generated by the VCO was used. The division by 120 in the feedback path is done with a cascade constituted by one half divider, implemented with a true single phase clock (TSPC) logic [8], and one divider by 30, followed by a toggle flip-flop to ensure a duty-cycle of 50% at the PFD input. The TSPC logic was used to overcome the impossibility to implement the first toggle flipflop with static logic in this technology.…”

Section: Frequency Synthesizermentioning

confidence: 99%

A 2.4-GHz wireless sensor network for smart electronic shirts integration

Carmo

Mendes

Afonso

et al. 2007

2007 IEEE International Symposium on Industrial Electronics

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Abstract-A typical sensing module is composed of sensors, interface electronics, a radio-frequency (RF) CMOS transceiver and an associated antenna. A 2.4-GHz RF transceiver chip was fabricated in a UMC 0.18 μm CMOS process. The receiver has a sensibility of -60 dBm and consumes 6.3 mW from a 1.8 V supply. The transmitter delivers an output power of 0 dBm with a power consumption of 11.2 mW. Innovative topics concerning efficient power management was taken into account during the design of the transceiver. A solution of individual sensing modules allows a plug-and-play solution. The target application is the integration of a wireless sensor network in smart electronic shirts, for monitoring the cardio-respiratory function and posture.

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A 13.5-mW 5-GHz Frequency Synthesizer With Dynamic-Logic Frequency Divider

Cited by 185 publications

References 15 publications

A 2.4 GHZ Wireless Electronic Shirt for Vital Signals Monitoring

A 2.4 GHZ Wireless Electronic Shirt for Vital Signals Monitoring

A 2.4 GHz fractional-N PLL with a low-power true single-phase clock prescaler

A 2.4-GHz wireless sensor network for smart electronic shirts integration

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