A 13-b 10-Msample/s ADC digitally calibrated with oversampling delta-sigma converter

Shu, Tzi-Hsiung; Song, Bang‐Sup; Bacrania, K.

doi:10.1109/4.375965

Cited by 65 publications

(1 citation statement)

References 16 publications

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“…ThedesignprincipleofΣ-△oversamplingADCiselaboratedbelow:△isfromthedifferencefrom theanaloginputsignalandtheoutputofDAC.Σistheturntheresultof△intointegral.Theresult comparedwithreferencevoltagewilldeterminewhetherornottheoutputof1-bitADCishigh.To improveresolutionofADC,theoutputstreamissmoothedbydigitalfiltering,whichisthebasisof oversampletechnique.ThetheoreticalmaximummultiplesofΣ-△modulatorare64-256multiples to convert rate (Shu, 1995). Based on variables analysis in Equation 1, an effective method to enhanceresolutionofΣ-△modulator,i.e.,SNR dB ,istoincreaseorderoftheloopfilterL.Additional integratorsandfeedbackpathscanbeaddedtothebasicoffirstordermodulator (Johnston,2001).…”

Section: Work For σ-△ Oversampling Adc Architecturementioning

confidence: 99%

Optimizing for High Resolution ADC Model With Combined Architecture

Ding

Liu

2020

International Journal of Cognitive Informatics and Natural Intelligence

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High resolution analog-digital conversion (ADC) is a key instrument to convert analog signals to digital signals, which is deployed in data acquisition system to match high resolution analog signals from seismometers systems. To achieve high resolution, architecture of Σ-△ oversampling or pipeline ADC architecture have following disadvantages: high power consumption, low linearity of modulators, and complex structure. This work presents a novel model architecture, which design principle is validated by mathematical formulations which combined advantages of both pipeline and Σ-△oversampling ADC architecture. By discussing the adverse effects of the whole ADC architecture with an external noise theoretically, an amended theoretical model is proposed according to the assessment result of a noise simulation algorithm. The simulation results represent that the whole performance of combined architecture is determined by the noise level of integrator and subtractor. Using these two components with a noise index no more than 10-7 V/√Hz, the resolution of the prototype can achieve a reservation of 144.5 dB.

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Section: Work For σ-△ Oversampling Adc Architecturementioning

confidence: 99%