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Power and area saving concepts such as operational amplifier (opamp) bias current reuse and capacitive level shifting are used to lower the analog power of a 10-bit pipelined analog-to-digital converter (ADC) to 220 W/MHz. Since a dual-input bias current reusing opamp performs as two opamps, the opamp summing nodes can be reset in every clock cycle. By using only N-channel MOS (NMOS) input stages, the capacitive level shifter simplifies the gain-boosting amplifier design and enables fast opamp settling with low power-consumption. The prototype achieves 9.2/8.8 effective number of bits (ENOB) for 1-and 20-MHz inputs at 50 MS/s. The ADC works within the temperature range of 0 to 85 C and the supply voltage from 1.62 to 1.96 V with little measured loss in the ENOB. The chip consumes 18 mW (11 mW for the analog portion of the ADC and 7 mW for the rest including buffers) at 1.8 V, and the active area occupies 1 1 1 3 mm 2 using a 0.18-m complementary metal oxide semiconductor (CMOS) process.Index Terms-Capacitor-array multiplying digital-to-analog converter (MDAC), digital-to-analog converter (DAC), low-power technique, opamp-sharing, pipelined analog-to-digital converter (ADC), switched-opamp.

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