A 14-b linear capacitor self-trimming pipelined ADC

Ryu, Seung‐Tak; Ray, S.; Song, Bang‐Sup; Cho, Gyu‐Hyeong; Bacrania, K.

doi:10.1109/jssc.2004.835823

Cited by 40 publications

(5 citation statements)

References 11 publications

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“…10 resolution and is very close to the value of the 14-bit resolution ADC in Ref. [3]. The FOM (figure of merit) of this work is only higher than that of Ref.…”

Section: Measured Resultssupporting

confidence: 82%

A 12-bit 40 MS/s pipelined ADC with over 80 dB SFDR

et al. 2010

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This paper describes a 12-bit 40 MS/s calibration-free pipelined analog-to-digital converter (ADC), which is optimized for high spurious free dynamic range (SFDR) performance and low power dissipation. With a 4.9 MHz sine wave input, the prototype ADC implemented in a 0.18-m 1P6M CMOS process shows measured differential nonlinearity and integral nonlinearity within 0.78 and 1.32 least significant bits at the 12-bit level without any trimming or calibration. The ADC, with a total die area of 3.1 2.1 mm 2 , demonstrates a maximum signal-to-noise distortion ratio (SNDR) and SFDR of 66.32 and 83.38 dB, respectively, at a 4.9 MHz analog input and a power consumption of 102 mW from a 1.8 V supply.

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“…10 resolution and is very close to the value of the 14-bit resolution ADC in Ref. [3]. The FOM (figure of merit) of this work is only higher than that of Ref.…”

Section: Measured Resultssupporting

confidence: 82%

A 12-bit 40 MS/s pipelined ADC with over 80 dB SFDR

et al. 2010

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“…In applications, the error of measuring results in the biggest impact, therefore, we need to calibrate all quantitative borders in ADC to make sure of the high precision of the measurement results. [50] In experiments, inevitably noise of the circuit itself and additive noise [51] will be added to the measured results, which leads to a small jitter in the actual conversion border and it has higher instability than the actual stability. So the quantitative random deviation of the border value should be taken into account in data processing and by selecting subsequent values at the borders, we can get rid of the interference of random noise [47][48][49] to make it closer to the border of its true position.…”

Section: Summary and Discussionmentioning

confidence: 99%

ADC border effect and suppression of quantization error in the digital dynamic measurement

Bai¹,

Liu²,

Zhou³

et al. 2017

Chinese Phys. B

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The digital measurement and processing is an important direction in the measurement and control field. The quantization error widely existing in the digital processing is always the decisive factor that restricts the development and applications of the digital technology. In this paper, we find that the stability of the digital quantization system is obviously better than the quantization resolution. The application of a border effect in the digital quantization can greatly improve the accuracy of digital processing. Its effective precision has nothing to do with the number of quantization bits, which is only related to the stability of the quantization system. The high precision measurement results obtained in the low level quantization system with high sampling rate have an important application value for the progress in the digital measurement and processing field.

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“…In addition, a fast background calibration is proposed which needs less than 0.5 s to converge, much faster than Refs. [11,15,17]. All these techniques guarantee the high performance of the proposed ADC while consuming only 166 mW power at Nyquist rate.…”

Section: Introductionmentioning

confidence: 88%

“…[11], and 60 times than Refs. [15,17]. Besides, unlike correlation-based algorithms OE12 , this background calibration does not affect the dynamic range of MDAC.…”

Section: Background Calibrationmentioning

confidence: 99%

“…Several previous works propose some improvements to get good linearity performances for high-speed 14-bit pipeline ADC, e.g. Reference [15] uses a pseudorandom dithering for capacitor calibration and Reference [17] needs an on-chip memory to store the error codes for calibration also getting the required static linearity. However, in these works, the calibration needs more than one minute to attain the convergence which is not suitable for many shortlatency applications.…”

Section: Introductionmentioning

confidence: 99%

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A 1.8 V low-power 14-bit 20 Msps ADC with 11.2 ENOB

Chen¹

2012

J. Semicond.

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This paper describes the design of a 14-bit 20 Msps analog-to-digital converter (ADC), implemented in 0.18 m CMOS technology, achieving 11.2 effective number of bits at Nyquist rate. An improved SHA-less structure and op-amp sharing technique is adopted to significantly reduce the power. The proposed ADC consumes only 166 mW under 1.8 V supply. A fast background calibration is utilized to ensure the overall ADC linearity.

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A 14-b linear capacitor self-trimming pipelined ADC

Cited by 40 publications

References 11 publications

A 12-bit 40 MS/s pipelined ADC with over 80 dB SFDR

A 12-bit 40 MS/s pipelined ADC with over 80 dB SFDR

ADC border effect and suppression of quantization error in the digital dynamic measurement

A 1.8 V low-power 14-bit 20 Msps ADC with 11.2 ENOB

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